Schematics

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0
1
GPIO19
(BOOT_SEL3)
0
0 SPI FLASH or EEPROM(CS1 must be used for boot device)
0
1 1
0
GPIO3
(BOOT_SEL1)
UART_TX
(BOOT_SEL0)
1
Strap Pin Setting Table
SPI NAND (SLC type, ECC in NAND device)
1
0
1
1
0
0
ONFI compliant NAND
BE-NAND
OFF = 0 ; ON = 1
BOOT_SE L2
BOOT_SE L3
ENDIAN_ SEL
VDSL DGSP Reset Buffer
Green Line need to connect
to GND directly.
EJTAG
1
Boot Source
0
0
0
0
UART w/o EEPROM
1
0
0
1
0
1
GPIO14
(BOOT_SEL2)
Legacy NAND (up to 2K page)
UART with EEPROM
1
1
1
0
0
1
All other options are reserved/not used.
Generic(non-ONFI) NAND
Endian SEL (For CPU)
0:LITTL E ENDIAN
1:BIG E NDIAN(Default)
NOTE:
Boot Strap
BOOT_SE L1
BOOT_SE L0
SENSE+/- routing on PCB
should be differentially and
Keep distance to switching
sensitive component,eg.
inductors.
AND
Gate
From button
to RX350
If DGSP reset then WiFi reset
Boot from SPI Flash
Manual Reset
WPS Button
2-Layer PUSH
POR_OUT Buffer
Reset
IC
UART
for EVB FW USE
DrayTek ICE
for 654 EVB FW
for 654 EVB FW
UART0_TX
EJTAG_TMS_U
LED_D GPIO5
RST_TO_DEFAULT_1
EJTAG_TDI_U
EJTAG_TDO_U
EJTAG_TMS_U
EJTAG_TCK_U
EJTAG_TDO_U
EJTAG_TCK_U
EJTAG_TRST_U
EJTAG_TDI_U
GPIO1 8
GPIO17
GPIO1 6
UART0_RX
SENSE+
EJTAG_TRST_U
GPIO9
DGSP_RST
SLIC_RESET
RST_TO_DEFAULT
RST_TO_DEFAULT_1
DGSP_RST
PCIE2_RST
PCIE2_RST_M
PCIE1_RST
PCIE2_RST_MDGSP_RST
PCIE2_RST
DGSP_RST
PCIE1_RST_M
DGSP_RST
PCIE1_RST
DGSP_RST
SLIC_RESET
SLIC_TX
SLIC_RX
SLIC_CLKO_GNT
SLIC_TX
SLIC_CLKO_GNT
SLIC_RESET_M
GPIO1 4
GPIO19
GPIO3
GPIO3
POR_OUT
RST_TO_DEFAULT
DGSP_RST SLIC_RESET_M
SLIC_RESET
PCIE1_RST_M
NETC2 90 _1
USB1_CTRL
GPIO4
GPIO6
USB2_CTRL
GPIO2 1
UART1_TX
UART1_RX
GPIO1 5
DGSP_RST
UART1_TX
GPIO5 LED_ D
GPIO19
GPIO14
RST_TO_DEFAULT_1
GPIO2 2
POR _OUT
S1_Bu ttom
WPS
RST_TO_DEFAULT
POR_OUT POR _OUT_4
RESET_IN
RESET_IN
+3V3
POR_OUT
USB1_CTRL
USB2_CTRL
POR_OUT
POR_OUT
POR _OUT_4
WPS
UART0_TX
UART0_RX
GPIO34
GPIO17
GPIO1 8
GPIO1 6
UART0_RX
RESET_IN
EJTAG_TRST_U
EJTAG_TDO_U
EJTAG_TDI_U
EJTAG_TMS_U EJTAG_TCK_U
S1_TOP
SENSE-
+3V3
GND
+3V3
+3V3
+3V3
GND
VDD33
+3V3
GND
+3V3
GND
GND
GND
GND
GND
GND
+3V3
GND
GND
GND
GND
GND
GND
+3V3
+3V3
GNDGND
+3V3
+3V3
GND
+3V3
+3V3
GND
+3V3
+3V3
GND
+3V3
+3V3
+3V3
GND
GND
SEN SE- [32]
SEN SE+ [32]
SLIC_CL KO_ GNT[12]
SLIC_TX[12 ]
PCIE1_ RST_M [16]
SLIC_RESET_ M [12 ]
DGSP_RST[1 3,27]
PCIE2_ RST_M[26 ]
LED_ ST[10]
LED_ D[10]
LED_ SH[10]
POR _OUT[9]
SPI_ DIN[8,10]
SPI_ Fla s h_ CS1[8]
SPI_ DOUT[8,10]
SPI_ CL K[8,10]
PCIE1_ RST [10,16]
PCIE2_ RST[10,16]
SFP_ I2C _DATA[24,33]
SFP_ I2C _CLK[24,33]
POR _OUT_4 [10 ]
USB2_PWR_ CTRL [9]
USB1_PWR_ CTRL [9,26]
GPIO1 8_ RS T[8,10]
GPIO1 7_ RS T[8,10]
GPIO1 6_ RS T[8,10]
SLIC_CL K[1 2]
SLIC_RX[12]
RST_TO_ DEFAUL T_AXE[16]
PCIE1_ RST_N_AXE[12]
Title
Size Docum ent N umber Rev
Date: Sheet of
GRX350_GPIO
6B
V2765AX_V1
<Org Nam e >
Cu s tom
7 34Frid ay, De cem be r 17, 20 21
Title
Size Docum ent N umber Rev
Date: Sheet of
GRX350_GPIO
6B
V2765AX_V1
<Org Nam e >
Cu s tom
7 34Frid ay, De cem be r 17, 20 21
Title
Size Docum ent N umber Rev
Date: Sheet of
GRX350_GPIO
6B
V2765AX_V1
<Org Nam e >
Cu s tom
7 34Frid ay, De cem be r 17, 20 21
S3
WPS Button / SW
S3
WPS Button / SW
1 2
3 4
C16
NULL/10uF
C16
NULL/10uF
T P5 1T P5 1
R56
10k,1%
R56
10k,1%
R2 79 2 2KR 27 9 22K
T P4 7T P4 7
R58 Null/1k,1%R58 Null/1k,1%
T P8T P8
R6 6 Null /0R6 6 Null /0
U1 5A
74 LVC08/SO
U1 5A
74 LVC08/SO
1
2
3
D3
SK2 4A
D3
SK2 4A
21
R239
10k,1%
R239
10k,1%
N.M.
R128
Null/1k,1%
N.M.
R128
Null/1k,1%
R235
NULL/1k,1%
R235
NULL/1k,1%
R244 10k,1% R244 10k,1%
U1 5C
74 LVC08/SO
U1 5C
74 LVC08/SO
9
10
8
C1 04
0.1uF/060 3
C1 04
0.1uF/060 3
C17 NULL/470pFC17 NULL/470pF
R237 Null/10k,1%R237 Null/10k,1%
Y1
40Mhz SMD 3.2x 2.5 10ppm
Y1
40Mhz SMD 3.2x 2.5 10ppm
13
2 4
T P3 9T P3 9
C29
100nF
C29
100nF
R6 7
10K
R6 7
10K
R1 71 3 3R1 71 3 3
R236
10k,1%
R236
10k,1%
R50 0R R50 0R
R6 4 33 RR6 4 33 R
1 2
R73 0R R73 0R
T P4 8T P4 8
T P4 1T P4 1
R59 10k,1% R59 10k,1%
R120
1k,1%
R120
1k,1%
T P6T P6
R5 3 0R5 3 0
R243 Null/10k,1% R243 Null/10k,1%
R133
1k,1%
R133
1k,1%
R52
47k,1%
R52
47k,1%
U1 5B
74 LVC08/SO
U1 5B
74 LVC08/SO
4
5
6
C69
100nF
C69
100nF
R72 0R R72 0R
N.M.
R74
Null/0R
N.M.
R74
Null/0R
T P1 1T P1 1
R1 74
4.7K
R1 74
4.7K
R60
Null/10k,1%
R60
Null/10k,1%
T P4 6T P4 6
T P9T P9
T P7T P7
R231
1k,1%
R231
1k,1%
N.M.
R135
Null/1k,1%
N.M.
R135
Null/1k,1%
R61 Null/10k,1%R61 Null/10k,1%
R6 2
(V)220o hm /Bead
R6 2
(V)220o hm /Bead
1 2
T P4 0T P4 0
C19 NULL/33pFC19 NULL/33pF
R127
1k,1%
R127
1k,1%
R238 1k,1% R238 1k,1%
R1 75 3 3R1 75 3 3
C24
10pF
C24
10pF
U2 1
MIC80 9SU
U2 1
MIC80 9SU
GND
1
/RST
2
VCC
3
R6 5 0/0 40 2R65 0/0402
R6 3
(V)220o hm /Bead
R6 3
(V)220o hm /Bead
1 2
R79
1k,1%
R79
1k,1%
R2 75
1K/0603
R2 75
1K/0603
R48 NULL/0R R48 NULL/0R
N.M.
R71
Null/0R
N.M.
R71
Null/0R
N.M.
R54
Null/0R
N.M.
R54
Null/0R
J8
He ad er 1x4/2.54mm
J8
He ad er 1x4/2.54mm
P1
1
P3
3
P2
2
P4
4
S2
De fau lt Bu tton / SW
S2
De fau lt Bu tton / SW
1 2
3 4
R172
10 K
R172
10 K
C3 00
0.1uF/25V
C3 00
0.1uF/25V
T P4 9T P4 9
R136
1k,1%
R136
1k,1%
R75
10k,1%
R75
10k,1%
C1 65 0.1uF/25VC1 65 0.1uF/25V
R122
1k,1%
R122
1k,1%
N.M.
R49 Null/0R
N.M.
R49 Null/0R
C23
10pF
C23
10pF
U5 F
GRX350
U5 F
GRX350
XTAL1
AC10
GPIO42
E20
GPIO43
D20
GPIO3/CLKO25
Y18
GPIO6/LED_SH/PHY4_LED0
Y9
GPIO5/LED_D/PHY3_LED0
AA8
D1V15SN
J8
POR
AA9
HRST
AA10
GPIO21/I2C_SDA
W10
GPIO4/LED_ST/PHY2_LED0
AB8
GPIO17/SPI0_TX
W6
GPIO22/I2C_SCL
W11
GPIO15/SPI0_CS1
Y5
GPIO14/SPI1_CS0/PHT6F_LED0
AB7
GPIO11/SPI1_RX/SPI0_CS6
AA7
UART0_TX
W9
GPIO10/SPI1_TX/SPI0_CS4
AB6
GPIO19/SPI1_CLK/PHY3_LED1
W8
TDO/EJ_TDO
E8
TCK/EJ_TCK
D8
UART1_TX
R8
GPIO16/SPI0_RX
W7
TDI/EJ_TDI
C9
UART0_RX
Y8
UART1_RX
P8
TMS/EJ_TMS
D9
TRST/EJ_TRST
C10
GPIO18/SPI0_CLK
Y6
GPIO1/SSI_RST
AA5
GPIO9/PHY5_LED0
AB4
GPIO8/CLK_O8/FL_CS0/PHY2_LED1
AB5
GPIO0
AB3
XTAL2
AB10
GPIO36/SSI_CLKI
AC4
GPIO35/SSI_RX
AA6
GPIO34/SSI_TX
Y7
GPIO7/CLKO40/USB_OC0_INT
Y10
GPIO2/USB_OC1_INT
Y11
D1V15SP
H8
W_GPIO0
T11
CLK_MD
AB9
TEST_N
AB11
TEST_P
AC11
C1 07
0.1uF/060 3
C1 07
0.1uF/060 3
U1 5D
74 LVC08/SO
U1 5D
74 LVC08/SO
12
13
11
U3
NULL/SN74HC08/SSOP14
U3
NULL/SN74HC08/SSOP14
1A
1
2B
5
3B
10
3A
9
3Y
8
1Y
3
2Y
6
GND
7
1B
2
2A
4
4Y
11
4A
12
4B
13
Vcc
14
T P1 0T P1 0
S3-1
TACT SWITCH CAP
S3-1
TACT SWITCH CAP
T P3 8T P3 8
R240
4.7k,1%
R240
4.7k,1%
J5
Nu ll/HEADER/2*5P/2 .54
J5
Nu ll/HEADER/2*5P/2 .54
P1
1
P2
2
P3
3
P4
4
P5
5
P6
6
P7
7
P8
8
T P5 0T P5 0
R2 45
33 R
R2 45
33 R
1 2
R176
10 K
R176
10 K