Specifications

This is the Title of the Book, eMatter Edition

454

Chapter 15: Memory Mapping and DMA

Obviously, a great deal of detail has been left out of this example, including what-

ever steps may be required to prevent attempts to start multiple, simultaneous DMA

operations.

DMA for ISA Devices

The ISA bus allows for two kinds of DMA transfers: native DMA and ISA bus mas-

ter DMA. Native DMA uses standard DMA-controller circuitry on the motherboard

to drive the signal lines on the ISA bus. ISA bus master DMA, on the other hand, is

handled entirely by the peripheral device. The latter type of DMA is rarely used and

doesn’t require discussion here, because it is similar to DMA for PCI devices, at least

from the driver’s point of view. An example of an ISA bus master is the 1542 SCSI

controller, whose driver is drivers/scsi/aha1542.c in the kernel sources.

As far as native DMA is concerned, there are three entities involved in a DMA data

transfer on the ISA bus:

The 8237 DMA controller (DMAC)

The controller holds information about the DMA transfer, such as the direction,

the memory address, and the size of the transfer. It also contains a counter that

tracks the status of ongoing transfers. When the controller receives a DMA

request signal, it gains control of the bus and drives the signal lines so that the

device can read or write its data.

The peripheral device

The device must activate the DMA request signal when it’s ready to transfer

data. The actual transfer is managed by the DMAC; the hardware device sequen-

tially reads or writes data onto the bus when the controller strobes the device.

The device usually raises an interrupt when the transfer is over.

The device driver

The driver has little to do; it provides the DMA controller with the direction, bus

address, and size of the transfer. It also talks to its peripheral to prepare it for

transferring the data and responds to the interrupt when the DMA is over.

The original DMA controller used in the PC could manage four “channels,” each

associated with one set of DMA registers. Four devices could store their DMA infor-

mation in the controller at the same time. Newer PCs contain the equivalent of two

DMAC devices:

the second controller (master) is connected to the system proces-

sor, and the first (slave) is connected to channel

0 of the second controller.

†

* These circuits are now part of the motherboard’s chipset, but a few years ago they were two separate 8237

chips.

† The original PCs had only one controller; the second was added in 286-based platforms. However, the sec-

ond controller is connected as the master because it handles 16-bit transfers; the first transfers only eight bits

at a time and is there for backward compatibility.

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