Specifications

G121SN01 V4 rev. 1.4
P
age 16/24
G
121SN01 V4
6.4 The Input Data Format
6.4.1 SEL68
SEL68 =“Low” or “NC” for 6 bits LVDS Input
SEL68 = “High” for 8 bits LVDS Input
Note1: Please follow PSWG.
Note2:
R/G/B data 7:MSB, R/G/B data 0:LSB
S
ignal Name Description
+RED7(R7)
+RED6(R6)
+RED5(R5)
+RED4(R4)
+RED3(R3)
+RED2(R2)
+RED1(R1)
+RED0(R0)
Red Data 7(MSB 8bit)
Red Data 6
Red Data 5 (MSB 6Bit)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
Red-pixel Data
Each red pixel’s brightness data consists of these
6/8 bits pixel data.
+GREEN7(G7)
+GREEN6(G6)
+GREEN5(G5)
+GREEN4(G4)
+GREEN3(G3)
+GREEN2(G2)
+GREEN1(G1)
+GREEN0(G0)
Green Data 7(MSB 8bit)
Green Data 6
Green Data 5 (MSB 6Bit)
Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
Green-pixel Data
Each green pixel’s brightness data consists of
these 6/8 bits pixel data.
+BLUE7(B7)
+BLUE6(B6)
+BLUE5(B5)
+BLUE4(B4)
+BLUE3(B3)
+BLUE2(B2)
+BLUE1(B1)
+BLUE0(B0)
Blue Data 7(MSB 8bit)
Blue Data 6
Blue Data 5 (MSB 6Bit)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
Blue-pixel Data
Each blue pixel’s brightness data consists of these
6/8 bits pixel data.
CLK Data Clock The typical frequency is 40MHz. The signal is used
to strobe the pixel data and DE signals.
All pixel data shall be valid at the falling edge when
the DE signal is high.
DE Display Timing This signal is strobed at the falling edge of CLK.
When the signal is high, the pixel data shall be valid
to be displayed.
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
NS
-
like format
AUO Confidential For DATAMODUL Internal Use Only / 2012/10/24
Data Modul AG - www.data-modul.com