Specifications

Copyright Peek Traffic Systems Incorporated, 2000
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INPUT FUNCTIONS CONTINUED…..
ABBREV BRIEF COMMENT/DESCRIPTION
OFF1-3 Offset inputs 1-3. Receives sync pulses from coord interconnect
TBC TBC On-line . No function in LMD, use interconnect inhibit
CTF Call to Free. Calls to free operation regardless of mode
SNCI Sync Inhibit. Disables sync pulses on offset outputs
CSYS Call to System operation input (interconnect mode)
TSNC Time Clock Sync input. Resets clock to programmable time
ITCI Interconnect Inhibit . Enables TBC (when programmed in auto mode)
AUTF UCF flash. Cycles to flash (see INIT/FL). Same as remote flash
CNAI/2 Call to non-act 1 and 2 inputs Places prog’d ph’s in CNA mode
FRC1/2 Force off R1-R2. Forces phase in ring to yellow if past min timings
IMX1/2 Inhibit Max inputs R1-R2. Allows phase in ring to extend indefinitely
MX21/2 Call to Max II R1-R2. Causes phase in ring to use Max II timings
ORC1/2 Omit Red Clear R1-R2. Causes phase in ring to skip red clear timing
PCY1/2 Ped Recycle inputs R1-R2. Allows phase in ring to recycle ped
RRM1/2 Red Rest Mode R1-R2. Ring rests in red if no calls (not last grn)
STM1/2 Stop Time inputs R1-R2. Causes all interval timers in ring to stop
CPR* Coord Ped Recycle (see CPR note)
UDA1-8 User defined alarm inputs 1-8 Can be logged, called in by system
ADR0-7 System address bits 0-7. Wired in cabinet, sets system address
VD33-64 Vehicle Detectors 33-64. Not currently supported by controller
PND1-6 Same as PRE inputs but ignore delay B4 PE timing
TPr1-6 Transit Priority request inputs. Calls for TP phase
TPrI Transit Priority Inhibit input. Disallows all Transit Priority operation
TPC1-6 Transit Priority Clear inputs. Clears TP call from memory
TIP1-8 TP Phase shorten inhibits. Disallows phase from being shortened by TP
OUTPUT FUNCTIONS
ABBREV BRIEF COMMENT/DESCRIPTION
PLNA Timing plan A output, driven by Clock ckt 1 (cyc 2) output
PLNB Timing plan B output, driven by Clock ckt 2 (cyc 3) output
PLNC Timing plan C output, driven by Clock ckt 6 (spl 2) output
PLND Timing plan D output, driven by Clock ckt 7 (spl 3) output
OFF1 Offset 1 output, driven by Clock ckt 3 (Offset 1) output
OFF2 Offset 2 output, driven by lock ckt 4 (Offset 2) output
OFF3 Offset 3 output, driven by Clock ckt 5 (Offset 3) output
OUTPUT FUNCTIONS CONTINUED…
ABBREV BRIEF COMMENT/DESCRIPTION
FLC Flash call (command). Active when flash called for
AUX1-4 Clock Aux (general) outputs Clock ckts 9-12
HOLD** Hold output. Active when coord ph hold applied (see note)
SYS System output. Active when system achieved (F.O’s active)
SYSC System command. Active when system called for
PE1-6 Pre-empt 1-6 outputs. Activated by PE programming
FL Flash Out. Active when Flash achieved
FLO Flashing Logic Out 1 hz DC squarewave output
CSA1 Coded Status Bit A, ring 1 See TDB pg 2-26, 3-11
CSB1 Coded Status Bit B, ring 1 See TDB pg 2-26, 3-11
CSC1 Coded Status Bit C, ring 1 See TDB pg 2-26, 3-11
CSA2 Coded Status Bit A, ring 2 See TDB pg 2-26, 3-11
CSB2 Coded Status Bit B, ring 2 See TDB pg 2-26, 3-11
CSC2 Coded Status Bit C, ring 2 See TDB pg 2-26, 3-11
FFL Fast Flash status output. Active when fast flashing
FFLO Fast Flash logic output. Pulses at fast flash rate
ADW1-8 Advance warning ph 1-8 outs See TDB pg 2-9, 4-5
ADWA-D Advance warning OL A-D outs See TDB pg 2-9, 4-5
SF1-24 Special Function outputs Allows MDM100 SF’s to be mapped to pins
CNT0-3 Display contrast bits 0-3. Do not change these--will lose cont. control
EL Display backlight control Do not change--will lose backlight control
CVMI Controller Voltage Mon inhib. Active when software disables CVM
FMI Fault Monitor inhibit Same as CVMI, but not active in planned (auto) FL
DS01-24 Detector simulator outputs. Allows outputs to be mapped to pins.
PEA1-6 Pre-empt acknowledge 1-6. Active upon receipt of PE call, even
during delay before pre-empt period.
*CPR NOTE
: When WRM = OFF and Ped Recycle = ON, CNA coord phases will
always go to Ped Clear upon the first permissive--regardless of demand. If there is
no demand, the CNA phase remains in green and eventually recycles the ped. CPR
determines when the ped gets recycled. When CPR input = OFF, the ped recycles
immediately after CNA ped clear. When CPR input = ON the CNA phase rests in
Green/Don’t Walk and allows the ped to recycle only after all permissives have
ended. Because the Coord Phase(s) remain green/Don’t Walk during permissive
periods, CPR allows more immediate response to conflicting demand.
**HOLD OUTPUT NOTE The LMD8000 had allowed an option to assign hold out to
MSD pin 48 or MSA pin d (phase 2 check). In the LMD9200 these are equivalent to
HOLD output I/O mapping codes 448 and 127 respectively. Be sure to zero out the
normal
function (such as assign 0 to phase 2 check) before assigning hold out to a
pin.