Specifications

Open Load
Open
Load
In
CS
ST
Tol,off
Tol,on
Vcs,H
Tol,off
Tcs, on2 Tcs, off1 Tcs, on1 Tcs, off2
In
Iout
Diag-En
CS
TPS1H100-Q1
SLVSCM2A –OCTOBER 2014–REVISED JANUARY 2014 www.ti.com
7.6 Timing Requirements – Current Sense Characteristics
(1)
MIN NOM MAX UNIT
CS settling time V
IN
= 5 V, I
load
≥ 5 mA. V
DIAG_EN
from 5 to 0 V. CS to 10% of sense
t
CS,off1
10 µs
from DIAG disabled value.
CS settling time V
IN
= 5 V, I
load
≥ 5 mA. V
DIAG_EN
from 0 to 5 V. CS to 90% of sense
t
CS,on1
10 µs
from DIAG enabled value.
V
DIAG_EN
= 5 V, I
load
≥ 5 mA. IN from 5 to 0 V. CS to 10% of sense
10 µs
CS settling time
value.
t
CS,off2
from IN falling edge
V
DIAG_EN
= 5 V, I
load
≥ 5 mA. IN from 5 to 0 V. Current limit triggered. 180 µs
CS settling time V
S
= 13.5 V, V
DIAG_EN
= 5 V, I
load
≥ 100 mA. V
IN
from 0 to 5 V. CS to
t
CS,on2
150 µs
from IN rising edge 90% of sense value.
(1) Value specified by design, not subject to production test.
Figure 3. CS Delay Characteristics
Figure 4. Open Load Blanking Time Characteristics
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