HogthrobV0 Users Manual Martin Leopold Technical Report no. 07/05 ISSN: 0107-8283 Dept.
HogthrobV0 Users Manual version 0.3 September 24, 2007 Martin Leopold Department of Computer science, University of Copenhagen Technical Report no.
0.1 0.2 0.3 Revision History Apr. 2006 Initial version Oct. 2006 Pin definitions Sep.
Contents 1 The Hogthrob Prototype Platform 1.1 Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 HogthrobV0 Overview 2.1 External Connections and Cables 2.1.1 Power . . . . . . . . . . . 2.1.2 Programming . . . . . . . 2.1.3 UART . . . . . . . . . . . 2.2 Pin Connections . . . . . . . . . . 2.2.1 ATMega-FPGA . . . . . . 2.2.2 ATMega-Radio . . . . . . 2.2.3 Bus Switches . . . . . . . 2.2.4 FPGA IO . . . . . . . . . . 5 6 . . . . . . . . . . . . . . . . . . .
. . . . . 24 24 24 25 25 5 Testing 5.1 AVR Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Fuse programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Program upload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 ATMega UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 ATMega LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5 ATMega push-buttons . . . .
Chapter 1 The Hogthrob Prototype Platform The Hogthrob prototype platform (HogthrobV0) must serve as a development platform throughout the Hogthrob project. It must be general enough to allow a large variety of configurations and robust enough to allow lab and field experiments. The platform was defined by the Hogthrob partners and was implemented by I/O Technologies delivering practical expertise in embedded systems design, PCB1 layout and assembly.
• A low-power timer • Add on-board with wireless communication • Add on-board with sensors • The ability be battery powered We choose to implement these goals using a Xilinx Spartan III FPGA with external FLASH for the FPGA configuration and for the program running on the FPGA. In addition we placed an ATMega 182l MCU that provides A/D as well as housekeeping for the FPGA power up/down procedure.
Chapter 2 HogthrobV0 Overview The functionality of the platform can be divided into four closely interacting subsystems: computing, sensing, communication, and power supply (see Figure 2.1).
Mother Board 3.0V Flash LP2989 Flash Memory 4M x 16 bit LED’s Spartan3 XC3S400 S P I PB’s Serial PROM 2 Serial PROM 1 J T A G nRF2401 PA U A R T 1 UART2 3.0V Flash Radio Board FPGA Core S P I 2.5V 1.2V MAX 192R UART2 2.5V MAX 192R Program Flash 128 KB I2C AVR Processor Core Sensors A/D SRAM 4KB Comp Sensor Board Clock 4MHz Bus Exchange Switches S P I U A R T 1 Frequency Synthesizer U A R T 1 3.0V Analog Crystal 16MHz Lowpass Filter fc=1.5MHz (max) JTAG 3.
(a) Motherboard (Picture and annotation by Kashif Virk) 9 (b) Layout
(a) J5 power connector (b) J1 programming connector Figure 2.3 Power and programming cables 2.1.2 Programming Connector J1 combines programming interfaces for the ATMega, FPGA and configuration PROMs (see figure 2.3(b)). Pin 16 has been cut and pin 16 has been blocked to provide a key for the correct placement of the connector. The two cables are combined into one that is connected to the appropriated programmers when programming either device. As depicted in Figure 2.
be connected to a PC. Some programmer boards such as the Atmel STK-5003 feature built in level conversion, however using a USB-RS232 converter can be convenient. Such a converter is usually built using a general purpose serial conversion chip such as Prolific PL-23034 or FTDI FT-2325 , the inputs on the chip can be connected to the UART output of the platform. 2.2 Pin Connections End point J1 J1 J1 J1 LED Button 2.2.
Line RXD1 TXD1 CLK (SCK) MOSI+MISO INT0 Radio Board J1, pin 31 J1, pin 32 CLK1 DATA DR2 Radio IO0 Radio IO1 Radio IO2 Radio IO3 Radio IO4 Radio IO5 Radio IO6 Radio IO7 Radio IO8 Radio IO9 Radio IO10 Radio IO11 2.2.
2.2.
Chapter 3 Xilinx FPGA The FPGA portion of the platform is controlled by the ATMega in a number of ways. The ATMega powers the FPGA on and off and points the radio interface to either the ATMega of FPGA. The FPGA boot procedure and ATMega dependence is described in Section 4.2 on page 20, the following describes the features that are independent of the ATMega. In order to program the FPGA the appropriate compiler must be installed see Section 3.2. 3.
3.1.3 Clock Source The FPGA has two external crystal clock sources: a 4 MHz and a 48 MHz source. The 4 MHz clock is always enabled, but the 48 MHz must be enabled by pulling I/O pin R10 high. 3.1.4 FPGA I/O A large number of the FPGA I/O pins have been connected to external connectors either with a dedicated purpose of as general purpose I/O. An example constrains file with appropriate naming for the external I/O pins is given in Appendix D on page 50, as well as [4].
requires you to run the installer as root. The installer is provided for Red Hat Linux, but it should work perfectly on most other distributions, except for the driver setup scripts. The installer contains scripts to setup the drivers at boot time and these are unlikely to be setup correctly outside of Red Hat. The installation script will also prepare an environment settings that you will need to load to start the tools. Depending on your shell this will look something like this: source ˜/Xilinx/setting.
3.2.2 ModelSim In addition to ISE it might be useful to simulate a project for debugging. For this purpose Xilinx provides ModelSim Xilinx Edition-III free of charge1 . Don’t forget to select the free ”Starter” version when installing. And be sure to select VHDL and not Verilog. The license file is then requested with a web link in the start menu. 3.
Chapter 4 ATMega In this section we will concern our selves with programming the features of the HTV0 board dealing with the ATMega. We will present programs them in C (see Appendix C) and construct TinyOS interface to control the features (see Section 4.4). 4.1 Hardware Setup The ATMega is powered on and boots a program from FLASH as soon as the board is powered up. It is then up to the ATMega program to turn on a, power up the FPGA and so forth.
Extended fuse High fuse 0xFF 0x00 0x8E Low fuse M103C OFF, WDTON OFF OCDEN ON, JTAGEN ON, SPIEN ON, CKOPT ON, EESAVE ON, BOOTSZ1 ON, BOOTSZ0 ON, BOOTRST OFF BODLEVEL OFF, BODEN ON, SUT1 ON, SUT0 ON CKSEL3 OFF, CKSEL2 OFF, CKSEL1 OFF, CKSEL0 ON Table 4.1 ATMega fuse settings (see [2, p.289] for further). The semantics of the fuse settings are reversed, meaning that a logical 1 corresponds to “off” and 0 to “on”.
cc V cc co V O n V DC− DC ATMega FPGA Figure 4.2 FPGA to ATMega interconnect. Each I/O pin of the FPGA is connected with two diodes for Electro-Static Discharge protection[5]. RF-AVR (1): RF-FPGA (2): A2-B2, A1-B1 RF(A2) to AVR (B2), Reset(A1) to FPGA(B1) A2-B1, A1-B2 RF(A2) to FPGA(B1), Reset(A1) to AVR(B2) The bus switches are controlled using 3 lines (RADIO MUX0/1/2) connected to AVR pins PC4/PC5/PC6.
MCUCR XMCRA XMCRB // 32 MCUCR &= ˜_BV(SRW10); // No wait-states = 0; // No wait-states = _BV(XMBK) | _BV(XMM0) | _BV(XMM1) |_BV(XMM2); kB address space w. bus-keeper |= _BV(SRE); // Enable external mem Figure 4.3 Configure and enable external memory if two proms are mounted it will probably not be possible to select the 2nd prom. In any case the line will be controlled by a pull-up resistor and leaving it will select the available PROM.
typedef struct \{ unsigned int rx_en : 1; unsigned int rf_ch : 7; unsigned int rf_pwr : 2; unsigned int xo_f : 3; unsigned int rfdr_sb : 1; unsigned int cm : 1; unsigned int rx2_en : 1; //high order bits \} __attribute__ ((packed)) typedef struct gen_config_t general_config; unsigned int crc_en:1; unsigned int crc_l:1; unsigned int addr_w:6; uint8_t addr1[5]; uint8_t addr2[5]; uint8_t data1_w; uint8_t data2_w; //uint8_t test[3]; // High order bits __attribute__ ((packed)) // // // // // // // RX or TX ope
lines — one outbound register and one inbound register. A transmission is initiated by putting a byte in the outbound register, starting the clock generator. Once the transmission is over the received data will reside in the inbound register. In our case, the MOSI and MISO lines are combined since we never receive data from and transmit data to the nRF2401 the same time. However it is still possible to utilize the SPI interface of the ATMega128l.
sendShockConfig rxMode txMode sendPkt samplePort dataReady HPLADC set fired HPLUART nRFSPI buttonInterrupt FPGAInterrupt sendDone dataReady Application htV0Control FPGASelProm FPGAPowerDown FPGAPowerOn radioMuxToAVR radioMuxToFPGA enableButtonInt disableButtonInt FPGAFlashBootOK get get print send StdOut On Off Timer LED’s Figure 4.5 TinyOS components 4.3.4 Direct Mode It should be possible to use the SPI unit to clock data in or out of the nRF2401.
In addition to this the ATMega128l based Mica variants and BTNode2 share the common meta platform avrmote — this platform provides only functionality related to the ATMega128l. The HogthrobV0 shares the same processor and we reuse as many components as possible. 4.4.2 FPGA, ATMega Interconnect The FPGA is connected to the ATMega128l through the external memory interface — from the ATMega the FPGA is merely memory mapped to a special portion of memory.
interface nRFSPI { command void enableSPIMaster(); /* Set up the nRF2401 in rx mode and provide a buffer for reception * The buffer must be atleast as big as ADDR_LEN and PAYLOAD_LEN * * The buffer is given back when the radio is set to txMode */ command void rxMode(nRF_pkt_t* pkt); /* Set the nRF2401 in tx mode and give back a buffer given in rxMode * of NULL if no buffer was given. */ command nRF_pkt_t* txMode(); /* Send a payload of "pkt" to the recipent in "pkt".
Chapter 5 Testing The goal of the following tests is to ensure that all the external interfaces (pin headers) and the on-board connections to the LED’s, Push Buttons, and all the chip-to-chip interfaces are working properly. The tests are to be performed one time only for each board ensuring a uniform assurance for each board. We will focus on the chip-to-chip interfaces and assume that unless we detect errors with the following tests the components are working.
nRF2400 Set one node as RX and one as TX and try to make them communicate The tests should be performed in the following order: The test sets the Bus-Switches (MUX) to point towards the AVR at boot-up. If this fails, the UART1 LED’s will not function. 5.1.1 Fuse programming The fuse setup particular features of the ATMega (see section 4.1.1). 1. Use UISP to program fuses 5.1.2 Program upload Test the program upload port (AVR-UART0, AVR→PEN). 1.
5.1.5 ATMega push-buttons Test the ATMega push button (AVR - Push-Button). 1. Test that the on-board Push-Button is connected to the AVR (PE7) 2. Upload the test program (the Push-Button test is enabled by default) 3. For each Push-Button press, the UART should report this. 5.1.6 ATMega radio connection and bus switches Test connection to the radio, this connection goes through the bus switches (AVR-nRF). Test that the Radio Transceiver is able to communicate through the connector to the Radio Board.
5.2.1 PROM Programming (Upload) Test JTAG and PROM-lines. 1. Connect JTAG and upload a configuration. 2. Read it back and see that the two are the same. 5.2.2 FPGA Boot (FPGA control-lines) Test that the FPGA↔AVR control-lines are correct and that the FPGA boots. 1. Upload the AVR program. 2. AVR sets the correct PROM () and powers up the FPGA (power on) - FPGA loads the program from the PROM. Set PROM SEL (It will be pulled-up now) AVR wait for the DONE Signal. Turn on the LED’s. 3.
5.2.5 AVR→FPGA Test that all the data and the control lines are working and that the FPGA can interrupt the AVR. The FPGA is connected to the AVR using the external SRAM interface (p. 26 in the AVR data sheet). Reading and writing to a register in the FPGA will test all the pins (AD, ALE, RD N, WE N). The latch and the register are implemented in the FPGA and the AVR writes and reads this register.
Appendix A Schematics 32
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A B C D R7 4.7K Device code 0x0 no dev 0x1 nRF2401 0x0 NC 0x0 NC VDD 5 R11 560R R5 560R R4 560R C7 33nF C11 22pF 16.
Appendix B Errata This chapter contains an errata from the HogthrobV0 Platform and Associated Documentation. • LED on MB and comm. board have different semantics • ŜS connected wrongly (should be unconnected) • Sensing and radio boards are connected to different sides of the MB PCB • J3 - 3.
B.2 Bill of Components • L3 might be changed to Murata LQH32CH15M11l (check index.htm) • The actual FLASH memory for the FPGA is unclear (stykliste and index.html are inconsistent) B.3 Schematics The schematic is out of date with the actual layout in several places. These mistakes refer to the schematic dated June 10 2004.
Appendix C FPGA control.c # define AVR ATmega128 1 # d e f i n e FALSE 0 # d e f i n e TRUE 1 # include # include # include # include
TOSH ASSIGN PIN ( UART TXD0 , E , 1 ) ; TOSH ASSIGN PIN (UART RXD1 , D, 2 ) ; TOSH ASSIGN PIN ( UART TXD1 , D, 3 ) ; / ∗ The FPGA i s c o n n e c t e d t o t h e AVR v i a t h e e x t e r n a l memory i n t e r f a c e ( o n l y t h e l o w e r a d d r e s s p i n s ) and an i n t e r r u p t pin ∗/ TOSH ASSIGN PIN (WE N, G, 0 ) ; TOSH ASSIGN PIN (RD N, G, 1 ) ; TOSH ASSIGN PIN (ALE, G, 2 ) ; TOSH ASSIGN PIN ( FPGA CS , C , 7 ) ; TOSH ASSIGN PIN (FPGA ON, D, 6 ) ; TOSH ASSIGN PIN (FPGA DONE, B , 4 ) ; / ∗ F
TOSH CLR FPGA CS PIN ( ) ; / / Doesn ’ t m a t t e r while ( ! TOSH READ FPGA DONE PIN ( ) ) { } ; } void FPGA off ( ) { TOSH MAKE FPGA ON OUTPUT ( ) ; TOSH MAKE FPGA CS OUTPUT ( ) ; TOSH CLR FPGA ON PIN ( ) ; TOSH CLR FPGA CS PIN ( ) ; } void toggleFPGA ( ) { i f ( FPGA running ) { FPGA running = FALSE ; FPGA off ( ) ; } else { FPGA running = TRUE ; FPGA on ( ) ; } } void setMuxToAVR ( ) { DDRC | = BV ( 2 ) ; DDRC | = BV ( 3 ) ; DDRC | = BV ( 4 ) ; DDRC | = BV ( 5 ) ; DDRC | = BV ( 6 ) ; DDRC | = BV ( 7 )
setMuxToAVR ( ) ; muxToAVR=TRUE ; } } / ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ ∗ ∗ LED TEST ∗ ∗ ∗ ∗ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ / / / Remeber .
TOSH MAKE MB LED OUTPUT ( ) ; TOSH MAKE RadioD1 LED OUTPUT ( ) ; TOSH MAKE RadioD2 LED OUTPUT ( ) ; / / S t a r t w i t h LEDs on ledsOn=TRUE ; TOSH SET MB LED PIN ( ) ; TOSH CLR RadioD1 LED PIN ( ) ; TOSH CLR RadioD2 LED PIN ( ) ; / / I t i s e x t r e m e l y i m p o r t a n t t h a t t h e p i n s g o i n g t o t h e FPGA / / a r e ” t r i s t a t e d ” w h i l e t h e FPGA i s o f f o r we r i s k c o n n e c t i n g / / an o u t p u t p i n d r i v i n g t h e l i n e d i r e c t l y t o ground // / /
Appendix D example.
NET ”WRI” LOC = ” t 3 ” NET ”FPGA INT6” NET ”FPGA CS” NET ”DONE” ; LOC = ”N5” ; LOC = ”P7” ; LOC = ”B14” ; # FPGA<−>F l a s h I n t e r f a c e NET ”Aout<0>” LOC = ”A5” NET ”Aout<1>” LOC = ”A7” NET ”Aout<2>” LOC = ”A3” NET ”Aout<3>” LOC = ”D5” NET ”Aout<4>” LOC = ”B4” NET ”Aout<5>” LOC = ”A4” NET ”Aout<6>” LOC = ”C5” NET ”Aout<7>” LOC = ”B5” NET ”Aout<8>” LOC = ”E6” NET ”Aout<9>” LOC = ”D6” NET ”Aout<10>” LOC = ”C6” NET ”Aout<11>” LOC = ”B6” NET ”Aout<12>” LOC = ”E7” NET ”Aout<13>” LOC = ”D7” NET ”Aout
# FPGA<−>Radio I n t e r f a c e NET ”FPGA IO0” LOC =”P15” NET ”FPGA IO1” LOC =”P14” NET ”FPGA IO2” LOC =”N16” NET ”FPGA IO3” LOC =”N15” NET ”FPGA IO4” LOC =”M14” NET ”FPGA IO5” LOC =”N14” NET ”FPGA IO6” LOC =”M16” NET ”FPGA IO7” LOC =”M15” NET ”FPGA IO8” LOC =”L13” NET ”FPGA IO9” LOC =”M13” NET ”FPGA IO10” LOC =”L15” NET ”FPGA IO11” LOC =”L14” NET ”FPGA IO12” LOC =”K12” NET ”FPGA IO13” LOC =”L12” NET ”FPGA IO14” LOC =”K14” NET ”FPGA IO15” LOC =”K13” NET ”FPGA IO16” LOC =” J 1 4 ” NET ”FPGA IO17” LOC =” J 1
NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO ” BIO 0” 1” 2” 3” 4” 5” 6” 7” 8” 9” 10 ” 11 ” 12 ” 13 ” 14 ” 15 ” 16 ” 17 ” 18 ” 19 ” 20 ” 21 ” LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC =”G2” =”C1” =”B1” =”C2” =”C3” =”D1” =”D2” =”E3” =”D3” =”E1” =”E2” =”F4” =”E4” =”F2” =”F3” =”G5” =”F5” =”G3” =”
Appendix E FPGA Makefile ## X i l i n x f p g a t o o l f l o w TOPDIR XDIR = .
XSTSCRIPT = $ ( PROJECT ) . x s t default : echo $ (XSTWORK) echo $ (SOURCES) . PRECIOUS : %.ngc %.ngc %.ngd %.map . ncd %. b i t %. par .
%.mcs : %. b i t $ (PROMGEN) −o $@ −w −p mcs −u 0 $< %.cmd : %. b i t > $@ echo ”setMode −bs ” >> $@ echo ” s e t C a b l e −p p a r p o r t 0 echo ” adddevice −p 1 −p a r t echo ” adddevice −p 2 − f i l e echo ”program −e −p 2 ” >> echo ” e x i t ” >> $@ # e c h o ” program −e −p 1 ” >> # e c h o ” i d e n t i f y ” >> $@ ” >> $@ x c f 0 2 s − f i l e $ ( PROJECT ) . mcs ” >> $@ $ ( PROJECT ) . b i t ” >> $@ $@ $@ program : $ ( PROJECT ) . cmd $ (IMPACT) −batch $ ( PROJECT ) .
Bibliography [1] Bootstrap demo design - users manual. URL http://www.oregano.at/ip/mc8051/ mc8051_bootstrap_ug.pdf. [2] Atmel. Atmega128(l) complete. URL http://www.atmel.com. [3] Martin Leopold, Mads Dydensborg, and Philippe Bonnet. Bluetooth and sensor networks: A reality check. In Proceedings of the First International Conference on Embedded Networked Sensor Systems, pages 103–113, November 2003. ISBN 1-58113-707-9. URL http://www. distlab.dk/public/distsys/publications.php?id=38. [4] Kashif Virk.
