Datasheet

DEP 20203-Y Production Specification
Version: 1 PAGE: 5
2. Interface Pin Function
Pin No. Symbol Pin Type Description
1 NC
－
No connection
2 VSL P This is segment voltage (output low level) reference pin.
When external VSL is not used, this pin should be left open.
When external VSL is used, connect with resistor and diode
to ground (details depend on application).
3 VSS P Ground pin. It must be connected to external ground.
4 REGVDD I Internal VDD regulator selection pin in 5V I/O application
mode.
When this pin is pulled HIGH, internal VDD regulator is
enabled (5V I/O application).
When this pin is pulled LOW, internal VDD regulator is
disabled (Low voltage I/O application).
5 SHLC I This pin is used to determine the Common output scanning
direction.
COM scan direction
SHLC COM scan direction
1 COM0 to COM31 (Normal)
0 COM31 to COM0 (Reverse)
Note
(1) 0 is connected to VSS
(2) 1 is connected to VDDIO
6 SHLS I This pin is used to change the mapping between the display
data column address and the Segment driver.
SEG scan direction
SHLS SEG direction
1 SEG0 to SEG99 (Normal)
0 SEG99 to SEG0 (Reverse)
Note
(1) 0 is connected to VSS
(2) 1 is connected to VDDIO
7 VDD P Power supply for core logic operation.
VDD can be supplied externally or regulated internally.
In LV IO application (internal VDD is disabled), this is a
power input pin.
In 5V IO application (internal VDD is enabled), VDD is
regulated internally from VDDIO.
A capacitor should be connected between VDD and VSS
under all circumstances.