Datasheet

DEP 128064J - Y - 12 -

9. Power ON / OFF Sequence & Application Circuit

9.1 POWER ON / OFF SEQUENCE

Power ON sequence:

1. Power ON V

DD.

2. After VDD become stable, set RES# pin LOW (logic low) for at least 3us(t1)

and then HIGH (logic high).

3. After set RES# pin LOW (logic low ), wait for at least 3us(t2).Then Power ON

VCC.(1)

4. After VCC become stable, send command AFh for display ON. SEG/COM wil

be ON after 100ms(tAF).

Power OFF sequence:

1. Send command AEh for display OFF.

2. Wait until panel discharges completely.

3. Power OFF V

CC. (1), (2)

4. Wait for tOFF. Power OFF VDD. (where Minimum tOFF=80ms, Typical

OFF=100ms )

Note:

(1) Since an ESD protection circuit is connected between VDD and VCC, VCC

becomes lower than VDD whenever VDD is ON and VCC is OFF as shown in

the dotted line of VCC in above figures.

(2)VCC should be disabled when it is OFF.