Specifications

C-7

C Buep 19e-Expander driver

P3: Name of the used timer for timeout (here: T0)

P4: Time value for timeout monitoring. Structure:

e.g. K4.2 = 4 seconds timeout

multiplication element 1 = 100 ms, 2 = 1 s

value

P5: General error message (bit, here M100.0)

The P5 general fault bit is set for any error in the connection between

the programmable controller and the PCS. This bit is automatically

reset as soon as the communication is running without a fault.

C1.3 Implementation of the software

The README.DOC/PROJECT.DOC files on the PCS 91.BOS floppy disk

contain current notes concerning the use of the various projects.

Implementation of the PLC software

• Equip the rack

• Set the block address on CPU and I/O boards

• Set the interface on the CPU and the SK (if possible set all to the

same parameters)

• Copy the corresponding project stored on the PCS 91.BOS floppy

disk to the hard disk

• Supply voltage to the PLC and the I/O boards

• Run the PLC programming software, select the project for the CPU,

enter the configuration in the SK table and transfer it into SK (under

LOADER).

• Transfer the PLC program into the controller using the loader (if

necessary, link in your application program and link newly)

• Connect PCS and PLC using an adapter cable described in section

3.6 (are the DIL-switch segments 5 and 6 at the PCS correspon-

dingly set?). The location for attaching the adapter cable is arbitrary.

How-ever, the block address must be correct and the communication

baud rate must correspond with the PCS.

• Set the E0.0 input to „1“

Now, the ERR LED (PCS) and the A0.0 output LED (PLC) must have

been deactivated. Also the 7-segment display at the SK must remain

dark. Thus, the communication is active.

Using this protocol, the addressed CPU can be accessed from an arbitrary

programming unit connector. This way, it is possible to manage several

PCSs by one CPU if each PCS is assigned it´s own communication block

and data block. However, it is possibly dangerous to assign several PCSs

to the same data block (the data transmitted by the PCS are then no

longer clearly alloca-table). A parallel mode of the programming unit and

the PCS is easily possible.