Technical information

SCI to SPI Peripheral Communication in V850ES Microcontrollers
Figure 29. Hardware Block Diagram
NEC
uPD70F3381Y
V850ES/KJ1+
LED-1 LED-2
SW2 SW3
PDH7 – PDH0
PDLH7 – PDLH0
(PDL15 – PDL8)
P94
P95
CE
SDI
SCLK
P915
P40/SI00
P42/SCK00
DS1722
P914
P41/SO00
Diode-Connected
NPN-Type Transistor
DxP
DxN
/CS
SDO
SCK
MAX6627
SDO
SERMODE
VCC
A
B
C
D
E
F
G
DP
LED-1 and LED-2
The µPD70F3318Y port pins for LED 1 and LED 2 are listed in Table 8. The PDL port is a 16-bit I/O
port. The upper eight bits of this port are used for LED-2. For 8-bit access, the upper part of PDL can be
referred to as PDLH; the I/O port bit PDLH.6 is the same as PDL.14 and uses the pin PDL14.
Table 8. Port Pins for LED1 and LED2
Segment LED1 LED2
A PDH0 PDL8 (PDLH0)
B PDH1 PDL9 (PDLH1)
C PDH2 PDL10 (PDLH2)
D PDH3 PDL11 (PDLH3)
E PDH4 PDL12 (PDLH4)
F PDH5 PDL13 (PDLH5)
G PDH6 PDL14 (PDLH6)
Decimal point PDH7 PDL15 (PDLH7)
Table 9. MCU Port Pins Used for Other I/O
I/O LED-1
SW2 input P94
SW3 input P95
MAX6627 chip select P915 (P9H.7)
DS1722 chip select P914 (P9H.6)
Serial Data In P40/SI00
Serial Data Out P41/SO00
Serial Clock P42/SCK00
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