Technical information

SCI to SPI Peripheral Communication in V850ES Microcontrollers

2.6.5 CSI00_SetType3(): Set CSI00 Peripheral for Type 3 Interface

The CSI00_SetType3() routine sets the CSI00 peripheral for type 3 interface, for use with the

DS1722 temperature sensor. First the CSI0E0 enable bit in the CSIM00 control register is cleared

to disable the CSI00 peripheral. This step is necessary when changing bits that control CSI00

operation.

Then in the CSIC0 clock control registers, the CKP0 (clock polarity) bit is set to 1 (SCK low when

idle), and the DAP0 bit (data phase) is cleared to zero (data driven on clock leading edge, data

input strobe on clock trailing edge). This sets Type-3 operation, equivalent to CPOL=0 and

CPHA=1 for SPI peripherals.

The CSI0E0 enable bit is set to one again, enabling CSI00 operation.

Figure 15. CSI00_SetType3(): Set CSI00 Peripheral for Type 3 Interface

CSI0E0 = 0 (CSIM00.7) to disableCSI0E0 = 0 (CSIM00.7) to disable

CKP0 = 1 (CSIC0.4)

DAP0 = 0 (CSIC0.3) for Type-3

CKP0 = 1 (CSIC0.4)

DAP0 = 0 (CSIC0.3) for Type-3

Return

CSI0E0 = 1 (CSIM00.7) to enableCSI0E0 = 1 (CSIM00.7) to enable

2.6.6 CSI00_SetType4(): Set CSI00 Peripheral for Type 4 Interface

The CSI00_SetType4() routine sets the CSI00 peripheral for type 4 interface, for use with the

MAX6627 temperature sensor.

First the CSI0E0 enable bit in the CSIM00 control register is cleared to disable the CSI00

peripheral. This step is necessary when changing bits that control CSI00 operation.

Then in the CSIC0 clock control registers, the CKP0 (clock polarity) bit is set to 1 (SCK low when

idle), and the DAP0 bit (data phase) is set to one (data input strobe on clock leading edge, data

driven out on clock trailing edge). This sets type 4 operation, equivalent to CPOL=0 and CPHA=0

for SPI peripherals.

The CSI0E0 enable bit is set to one again, enabling CSI00 operation.