Technical information

CSI to SPI Peripheral Communication in V850ES Microcontrollers

In the CSIC0 clock control register, the CKP0 (clock polarity) bit is set to one and the DAP0 (data

phase) bit is cleared to zero. This sets type 3 operation, equivalent to CPOL=0 and CPHA=1 for

SPI peripherals. Note that this will be changed by the CSI00_SetType4() routine, and restored by

the CSI00_SetType3() routine, to change modes depending on which SPI peripheral is accessed.

Figure 14. CSI00_Init(): Initialize Clocked Serial I/O 00 Peripheral

CSIM00 = 00H to disable CSI00

CSI0MK0 = 1 (CSI0IC0.6) mask int

CSIM00 = 00H to disable CSI00

CSI0MK0 = 1 (CSI0IC0.6) mask int

Return

CCL0 = 0 (CSIM00.5) for 8-bit

DIR0 = 0 (CSIM00.4) for MSB first

CCL0 = 0 (CSIM00.5) for 8-bit

DIR0 = 0 (CSIM00.4) for MSB first

PMC4.2-0 = 111

P42 pin set to SCK00 function

P41 pin set to SO00 function

P40 pin set to SI00 function

CKP0 = 1 (CSIC0.4)

DAP0 = 0 (CSIC0.3) for Type-3

CKP0 = 1 (CSIC0.4)

DAP0 = 0 (CSIC0.3) for Type-3

CKS002 – CKS000 = 001

(CSIC0.2-0) for fxx/4, 5 MHz

CKS002 – CKS000 = 001

(CSIC0.2-0) for fxx/4, 5 MHz

CSI0IC0.2-0 = 111 for lowest priority

CSI0MK0 = 0 (CSI0IC.5) enable int

CSI0IC0.2-0 = 111 for lowest priority

CSI0MK0 = 0 (CSI0IC.5) enable int

TRMD0 = 1 (CSIM0.6) for Tx/Rx

CSI0E0 = 1 (CSIM0.7) to enable

TRMD0 = 1 (CSIM0.6) for Tx/Rx

CSI0E0 = 1 (CSIM0.7) to enable

The lowest three bits of the CSIC0 clock control register set the clock to be used for the CSI00

peripheral. These are set to 001, to select the clock as fxx/4. Since the system clock is 20 MHz, this

setting produces a SCK frequency of 5 MHz, the maximum supported for the two peripherals used.

The interrupt control register CSI0IC0 is set for the lowest priority group, and the INTCSI00

interrupt is enabled by clearing the mask bit CSI0MK0.

In the CSIM0 control register, the TRMD0 bit is set to one to allow transmit/receive operation, and

finally the CSI0E0 enable bit is set to enable the CSI00 peripheral to operate.

At this point, the CSI00 peripheral is ready for operation. Writing a byte to the SOTB0L register

will begin data transmission and simultaneous reception.