User`s guide
Table Of Contents
- Contents
- Tables
- Preface
- Introduction
- Getting Started
- 2.1 Overview
- 2.2 Hardware Required
- 2.3 Hardware Debug Features
- 2.4 Setting Up the SROM Serial Port Connection
- 2.5 Starting and Running the Mini-Debugger
- 2.6 Sample Session on the EB64
- 2.7 Sample Session on the EB64+ and the AlphaPC 6...
- 2.8 Sample Session on the EB66 and EB66+
- 2.9 Sample Session on the EB164
- 2.10 Sample Session on the AlphaPC 164
- 2.11 Sample Session on the AlphaPC 164LX
- 2.12 Onboard Machine Check Handler
- SROM Mini-Debugger Command Set
- Support, Products, and Documentation
- Index
Getting Started 2–41
Sample Session on the AlphaPC 164LX
SROM> dm ! Set MCR (memory control register).
A> 8750000000
D> 3a1401
SROM> dm ! Set RTR again to force a
A> 8750000300
! refresh after the MCR has been set.
D> 750
! Set the memory bank registers for two banks of DIMMs totalling
! 128MB.
SROM> dm
! Set memory BBAR0
A> 8750000600
! (base address register 0).
D> 0
SROM> dm ! Set memory BBAR1.
A> 8750000640
D> 100
SROM> dm ! Set memory BTR0
A> 8750000a00
! (base timing register 0).
D> 22
SROM> dm ! Set memory BTR1.
A> 8750000a40
D> 22
SROM> dm ! Set memory BCR0
A> 8750000800
! (base configuration register 0).
D> 28
! Write once with the bank disabled.
SROM> dm ! Set memory BCR1.
A> 8750000840
D> 28
SROM> dm ! Set memory BCR0.
A> 8750000800
! Write a second time enabling the banks.
D> 29
SROM> dm ! Set memory BCR1.
A> 8750000840
D> 29