User`s guide

Getting Started 2–39
Sample Session on the AlphaPC 164LX
BBARQ-1 registers receive the base address bits [33:24] in bits [15:6]. BCR0-1
registers receive the bank size as in the following table:
Each BCR register is first written with the appropriate value from the preceding
table and then again with the low bit set to enable the banks.
5. Wake up memory by performing eight consecutive RAS cycles to each DIMM
side. This can also be done by writing the full memory range.
6. Turn on the Dcache, Bcache, and the secondary cache.
7. Initialize memory and the caches by writing to memory.
8. At this point, memory initialization is complete. If you want to perform I/O
tests, then you need to initialize that part of the system and:
a. Reset the ISA bus.
b. Configure SIO, enabling accesses to RTC, configuration RAM
(configuration jumpers), and flash ROM space.
c. Initialize the RTC clock in the SMC chipset.
2.11.1 AlphaPC 164LX Sample Log File
The following sample log file initializes the AlphaPC 164LX.
! AlphaPC 164LX Log.
!
! Flush Scache, set block size to 64 bytes
! and turn on set S0 only to facilitate memory
! accesses. Note that the Scache can’t
! be turned off completely.
Bank Size Register Value
16MB 2C
32MB 2A
64MB 28
128MB 26
256MB 24
512MB 22