User`s guide

2–22 Getting Started
Sample Session on the EB164
To initialize the EB164, follow these steps:
1. Flush the secondary cache (L2) and turn on only one set. The reason to flush the
secondary cache is to prevent any type of parity errors; only one set is turned on
to facilitate read operations that need to go all the way out to memory and not be
cached.
2. Turn off the Bcache to facilitate read operations that need to go all the way out to
memory and not be cached. The Bcache configuration register must have the
read and write speeds set to the ratio of the sysclock to CPU. Refer to the
chapter on configuration jumpers in the board’s user’s guide to determine this
ratio.
3. Initialize the CIA control register.
4. Initialize the CIA acknowledge register to disable the Bcache Victim Acknowl-
edge signal.
5. Initialize the memory control register. This register controls the refresh rate, and
memory width.
6. Set the bank timing registers. EB164 uses only one of these three registers.
7. Set MBA0, which controls the only memory bank in EB164. The value is
dependent on the amount of memory and type of SIMMs used. Refer to the
following table:
8. Wake up the memory by performing eight consecutive RAS cycles to each
SIMM side.
9. Turn on Dcache, Bcache, and all three sets in the secondary cache.
10. Initialize memory and the caches by writing to memory.
Memory Size SIMM Type MBA Value
32MB 1Mx36 (4MB) 10000011
64MB 2Mx36 (8MB) 10008011
128MB 4Mx36 (16MB) 10000073
256MB 8Mx36 (32MB) 10008073
512MB 16Mx36 (64MB) 100001F5