User`s guide
Table Of Contents
- Contents
- Tables
- Preface
- Introduction
- Getting Started
- 2.1 Overview
- 2.2 Hardware Required
- 2.3 Hardware Debug Features
- 2.4 Setting Up the SROM Serial Port Connection
- 2.5 Starting and Running the Mini-Debugger
- 2.6 Sample Session on the EB64
- 2.7 Sample Session on the EB64+ and the AlphaPC 6...
- 2.8 Sample Session on the EB66 and EB66+
- 2.9 Sample Session on the EB164
- 2.10 Sample Session on the AlphaPC 164
- 2.11 Sample Session on the AlphaPC 164LX
- 2.12 Onboard Machine Check Handler
- SROM Mini-Debugger Command Set
- Support, Products, and Documentation
- Index
Getting Started 2–19
Sample Session on the EB66 and EB66+
SROM> dm
A> 48 ! Bank Timing 1.
D> 645521
! For EB66+ use 68933.
SROM> dm
A> 50
! Bank Timing 2.
D> 645521
! For EB66+ use 68933.
SROM> dm
A> 58 ! Bank Timing 3.
D> 645521
! For EB66+ use 68933.
SROM> ba
00000001.20000000
BaseAddr OFF
! Perform 8 consecutive RAS cycles to each memory bank to “wake up” the
! DRAMs.
SROM> fm
A> 0
A> 20000000 ! Maximum memory size supported.
D> 0
! This may take several seconds.
! Load CAR to set Bcache timing, size, and disable ECC and parity.
! The exact BCache timing varies depending on CPU and cache RAM speeds.
! You can set the read and write speeds to a maximum value. For
! example, use 7f61 for a 512KB cache with maximum read and write speeds
! allowed.
SROM> dm
A> 120000078
D> 6b41
! Write enough locations to sweep the Bcache.
! Note that the Bcache is allocated on write operations.
SROM> fm
A> 0
A> 100000 ! Size of BCache.
D> 0