User`s guide
Table Of Contents
- Contents
- Tables
- Preface
- Introduction
- Getting Started
- 2.1 Overview
- 2.2 Hardware Required
- 2.3 Hardware Debug Features
- 2.4 Setting Up the SROM Serial Port Connection
- 2.5 Starting and Running the Mini-Debugger
- 2.6 Sample Session on the EB64
- 2.7 Sample Session on the EB64+ and the AlphaPC 6...
- 2.8 Sample Session on the EB66 and EB66+
- 2.9 Sample Session on the EB164
- 2.10 Sample Session on the AlphaPC 164
- 2.11 Sample Session on the AlphaPC 164LX
- 2.12 Onboard Machine Check Handler
- SROM Mini-Debugger Command Set
- Support, Products, and Documentation
- Index
2–18 Getting Started
Sample Session on the EB66 and EB66+
SROM> dm ! Set Global Timing Register (GTR) with
A> 60
! refresh enabled, bit [18] = 1.
D> 11343185
! Based on 70 ns SIMMs and 166 MHz CPU.
! See table for other CPU speeds.
! Configure the memory banks for the fully supported memory size.
SROM> dm
A> 0 ! BCR0.
D> 43c0
! Ignores ECC bit. Bank Base 0x0.
SROM> dm
A> 8 ! BCR1.
D> 80043c0
! Ignores ECC bit. Bank Base 0x8000000.
SROM> dm
A> 10 ! BCR2.
D> 100043c0
! Ignores ECC bit. Bank Base 0x10000000.
SROM> dm
A> 18
! BCR3.
D> 180043c0
! Ignores ECC bit. Bank Base 0x18000000.
SROM> dm
A> 20 ! BMR0. Set to max size bank size = 128MB.
D> 7f00000
SROM> dm
A> 28
! BMR1. Set to max size bank size = 128MB.
D> 7f00000
SROM> dm
A> 30 ! BMR2. Set to max size bank size = 128MB.
D> 7f00000
SROM> dm
A> 38
! BMR3. Set to max size bank size = 128MB.
D> 7f00000
SROM> dm
A> 40
! Bank Timing 0.
D> 645521
! Based on 70 ns SIMMs and 166 MHz CPU speed.
! For EB66+ use 68933 for 233 MHz CPU speed.