User`s guide

Getting Started 2–17
Sample Session on the EB66 and EB66+
The following table displays the BCR and BMR values for the selected bank
size.
In the EB66 sample log file shown in Section 2.8.1, there are two banks with
4MB×36 SIMMs for a total memory size of 64MB.
9. Write good parity and ECC to memory by writing all memory locations.
(memory size×1024×1024) –4. In the sample log file, this value is 3FFFFFC for
64MB of memory.
10. Initialize the error status register (ESR).
The ESR may have powered on with some error bits set, or error bits may have
been set while sweeping the Bcache. Write a 1 to all the write-1-to-clear bits to
initialize this register.
11. By default, the PCI bus is disabled. To enable access to the PCI bus and
configuration registers you must clear the PCI RST signal.
2.8.1 EB66 Sample Log File
The following sample log file initializes the EB66.
!
Sample EB66 initialization Log File.
!
Differences for EB66+ are noted in comment field.
V00001c01
SROM> sb
! Set base address for memory controller.
A> 120000000
00000001.20000000
BaseAddr ON
SROM> dm
! Ensure that the “Write wrong ECC” bits are
A> 68
! cleared in the Error Status Register.
D> 0
Bank Size SIMM Type BCR BMR
8MB 1MB×36 44C0 700000
16MB 2MB×36 64C0 F00000
32MB 4MB×36 45C0 1F00000
64MB 8MB×36 65C0 3F00000
128MB 16MB×36 47C0 7F00000