User`s guide
Table Of Contents
- Contents
- Tables
- Preface
- Introduction
- Getting Started
- 2.1 Overview
- 2.2 Hardware Required
- 2.3 Hardware Debug Features
- 2.4 Setting Up the SROM Serial Port Connection
- 2.5 Starting and Running the Mini-Debugger
- 2.6 Sample Session on the EB64
- 2.7 Sample Session on the EB64+ and the AlphaPC 6...
- 2.8 Sample Session on the EB66 and EB66+
- 2.9 Sample Session on the EB164
- 2.10 Sample Session on the AlphaPC 164
- 2.11 Sample Session on the AlphaPC 164LX
- 2.12 Onboard Machine Check Handler
- SROM Mini-Debugger Command Set
- Support, Products, and Documentation
- Index
2–16 Getting Started
Sample Session on the EB66 and EB66+
5. Load the cache control register (CAR) to set the Bcache timing and size as well
as to disable ECC and parity.
The following table displays the bank timing register (BTR) value for different
CPU speeds for 70-ns SIMMs:
6. Write all locations in Bcache.
The following table displays the memory range for the cache size:
7. Enable error checking in the Bcache.
8. Set the bank configuration registers (BCRx) and bank mask registers (BMRx) to
match what is on the motherboard.
CPU Speed
EB66
BTR Value
EB66+
BTR Value
66 MHz 0x00202200 0x00022311
100 MHz 0x00423310 0x00023411
166 MHz 0x00645521 0x00046722
200 MHz 0x00866721 0x00067833
233 MHz 0x00C67832 0x00068933
266 MHz 0x00C88932 0x0128AB44
300 MHz 0x02EAAB53 0x012ABC55
Cache Size Memory Range
256KB 0 → 40000
512KB 0 → 80000
1MB 0 → 100000