User`s guide

Getting Started 2–15
Sample Session on the EB66 and EB66+
2. Set the Global Timing Register (GTR). For example, if you use 70-ns SIMMs,
use the value from the following table, corresponding to your CPU speed:
3. Initialize the Bcache.
Configure the memory banks for the fully supported memory size to avoid any
illegal addresses that could cause the memory subsystem to fail to initialize all
backup cache entries. When the system is powered on, the backup cache
contains UNPREDICTABLE data in the tag RAMs. As the cache is swept for
initialization, the old blocks (called the dirty victim blocks) are written back to
main memory. These victim write operations occur based on the tags that store
the upper part of the address location for the dirty blocks of memory. These
UNPREDICTABLE tags cause victim write operations to UNPREDICTABLE
addresses in memory without regard to the quantity of memory actually
contained in the system.
4. Perform eight consecutive RAS cycles to each memory bank to “wake up” the
DRAMs.
This is done by reading (or writing) from each bank eight times. Space the read
operations 32KB apart to avoid page mode cycles. In the EB66 sample log file
shown in Section 2.8.1, this procedure is replaced by a fill-memory command to
the entire memory, which has the same effect but requires less typing.
Note that the caches are disabled at this point so that the read operations (and
write operations) go directly to the DRAMs.
CPU Speed
EB66
GTR Value
EB66+
GTR Value
66 MHz 0x007C10A1 0x007C10A2
100 MHz 0x10BC1CE3 0x00BC1CC3
166 MHz 0x11343185 0x01343146
200 MHz 0x21743DE7 0x01743DA6
233 MHz 0x21AC4629 0x11B445C8
266 MHz 0x31EC528A 0x11EC5249
300 MHz 0x322C5EEB 0x122C5EBA