User`s guide
Table Of Contents
- Contents
- Tables
- Preface
- Introduction
- Getting Started
- 2.1 Overview
- 2.2 Hardware Required
- 2.3 Hardware Debug Features
- 2.4 Setting Up the SROM Serial Port Connection
- 2.5 Starting and Running the Mini-Debugger
- 2.6 Sample Session on the EB64
- 2.7 Sample Session on the EB64+ and the AlphaPC 6...
- 2.8 Sample Session on the EB66 and EB66+
- 2.9 Sample Session on the EB164
- 2.10 Sample Session on the AlphaPC 164
- 2.11 Sample Session on the AlphaPC 164LX
- 2.12 Onboard Machine Check Handler
- SROM Mini-Debugger Command Set
- Support, Products, and Documentation
- Index
Getting Started 2–13
Sample Session on the EB64+ and the AlphaPC 64
A> 0 ! Enable Bcache, ignore tag, and allocate
D> 1b4
! on write operations.
SROM> dm
! Clear the Tag Enable Register.
A> 60
D> 0
SROM> ba
00000001.80000000
BaseAddr OFF
SROM> fm
! Write to entire cache to init cache
A> 0
! tags and data.
A> 200000
! Set this to BCache size = 2MB.
D> 0
SROM> ba
00000001.80000000
BaseAddr ON
SROM> dm
! Set Tag Enable Register to 2MB BCache.
A> 60
D> 3fe0
SROM> dm ! Clear the ignore tag bit previously set.
A> 0
D> b4
SROM> ba
00000001.80000000
BaseAddr OFF
SROM> dc
! Enable the BCache in the CPU. For
IPR> bctl
! AlphaPC 64 use 4E.4001.E645.
D> 4e4001e665
*BCTL 0000004e.4001e665
! At this point the BCache is initialized and enabled.
SROM> dc
! Enable DCache and machine checks.
IPR> abox
D> 42a
*ABOX 00000000.0000042a