User`s guide
Table Of Contents
- Contents
- Tables
- Preface
- Introduction
- Getting Started
- 2.1 Overview
- 2.2 Hardware Required
- 2.3 Hardware Debug Features
- 2.4 Setting Up the SROM Serial Port Connection
- 2.5 Starting and Running the Mini-Debugger
- 2.6 Sample Session on the EB64
- 2.7 Sample Session on the EB64+ and the AlphaPC 6...
- 2.8 Sample Session on the EB66 and EB66+
- 2.9 Sample Session on the EB164
- 2.10 Sample Session on the AlphaPC 164
- 2.11 Sample Session on the AlphaPC 164LX
- 2.12 Onboard Machine Check Handler
- SROM Mini-Debugger Command Set
- Support, Products, and Documentation
- Index
Getting Started 2–11
Sample Session on the EB64+ and the AlphaPC 64
3. Configure the Digital Semiconductor 21071-CA to use the Bcache tags, and set
the BIU_CTL register in the Alpha 21064 to enable the Bcache.
4. Enable the Dcache.
Before accessing the PCI bus on the EB64+, several registers in the Digital
Semiconductor 21071-DA must be initialized.
• The PCI Master Latency Timer must be set up before any PCI accesses are
attempted.
• The address extension registers (HAXRx) that are used for different types of PCI
accesses must also be initialized.
The EB64+ sample log file initializes HAXR2 before attempting a PCI configuration
cycle.
2.7.1 EB64+ Sample Log File
The following sample log file initializes the EB64+. A log file for the AlphaPC 64
would be the same with the exception of the BIU_CTL register. See the comments in
the log file.
! Sample EB64+ initialization Log file.
V00001c01
SROM> dc
! Turn BCache off by writing to BIU_CTL
IPR> bctl
! register. For AlphaPC 64 use 4E.4001.E644.
D> 4e4001e664
*BCTL 0000004e.4001e664
SROM> sb
! Set base for easier access to DC21071 regs.
A> 180000000
00000001.80000000
BaseAddr ON
SROM> dm
! Init Global Timing Register.
A> 200
D> 25
SROM> dm ! Init Refresh Timing Register.
A> 220
D> 444
SROM> dm ! Init Bank 0 Timing Register A.
A> c00