User`s guide

2–10 Getting Started
Sample Session on the EB64+ and the AlphaPC 64
2.7 Sample Session on the EB64+ and the AlphaPC 64
To run the mini-debugger on the EB64+ or the AlphaPC 64, set up the BIU_CTL
register with the backup cache (Bcache) disabled. For example:
BIU_CTL : 0000004E 4001E664 ! for EB64+
0000004E 4001E644 ! for AlphaPC 64.
After main memory is initialized, the Bcache can be enabled as shown in the EB64+
sample log. The example assumes a system with a 2MB Bcache. For a different
Bcache size, change bits [30:28] in the BIU_CTL register (refer to DECchip 21064
and DECchip 21064A Alpha AXP Microprocessors Hardware Reference Manual for
encoding) and the Tag Enable Register in the DECchip 21071 (see the DECchip
21071 and DECchip 21072 Core Logic Chipsets Data Sheet for encoding).
To initialize the memory controller for a 32-MB bank of memory in bank 0, the
following values must be loaded into the Digital Semiconductor 21071-CA memory
control registers:
Finally, all of memory must be written to initialize data parity.
To initialize and enable the Bcache, follow these steps:
1. Initialize the cache tag RAMs.
This is done by enabling the cache in the Digital Semiconductor 21071-CA and
configuring the Digital Semiconductor 21071-CA to ignore the tag, and to
allocate blocks in the cache on write operations.
2. Perform a memory write to every address from address 0 up to the size of the
cache.
This will load good data, tag, and tag control parity into the Bcache.
Register Data
Global Timing Register 00000025
Refresh Timing Register 00000444
Bank 0 Timing Register A 00002684
Bank 0 Timing Register B 00000C01
Bank 0 Base Address Register 00000000
Bank 0 Configuration Register 000000EB