Digital Semiconductor Alpha Microprocessors SROM Mini-Debugger User’s Guide Order Number: EC–QHUXC–TE Revision/Update Information: This is a revised document. It supersedes the Digital Semiconductor Alpha Microprocessors SROM Mini-Debugger User’s Guide (EC–QHUXB–TE). Digital Equipment Corporation Maynard, Massachusetts http://www.digital.
May 1997 While Digital believes the information included in this publication is correct as of the date of publication, it is subject to change without notice. Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description.
Contents Preface 1 Introduction 1.1 1.2 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1–1 Getting Started 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Required. . . . . . . . . . . . . . . .
3 SROM Mini-Debugger Command Set 3.1 3.2 3.3 3.4 A Support, Products, and Documentation Index iv Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command and User Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables 3–1 3–2 3–3 Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Register Names for the dc Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Register Names for the ec Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface Introduction This document describes how to use the Alpha Microprocessors SROM Mini-Debugger (also referred to as the mini-debugger) to debug hardware with one of the following evaluation boards: • The AlphaPC 164LX Motherboard (AlphaPC 164LX) • The AlphaPC 164 Motherboard (AlphaPC 164) • The Alpha 21164 Evaluation Board (EB164) • The AlphaPC 64 Motherboard (AlphaPC 64) • The Alpha 21066A Evaluation Board (EB66+) • The Alpha 21064 and 21064A PCI Evaluation Board (EB64+) • The Alpha 2106
Content Overview The information in this document is organized as follows: • Chapter 1 is a general overview of the mini-debugger. • Chapter 2 describes how to set up and start the mini-debugger. • Chapter 3 describes the mini-debugger command set. • Appendix A contains information about technical support services, products, and associated documentation.
1 Introduction 1.1 Overview The Alpha Microprocessors SROM Mini-Debugger provides basic hardware debugging capability through the SROM serial port of the Alpha microprocessor. Using only an SROM containing the mini-debugger, a clock source, a CPU chip, and a few gates, you can exercise the device connected to the CPU to debug cache, memory, and I/O subsystems until the board is functional enough to support a more fully featured monitor. 1.
2 Getting Started 2.1 Overview The Alpha Microprocessors Motherboard Software Design Tool Kit (Alpha SDK) includes the Alpha Microprocessors SROM Mini-Debugger binary files suitable for programming an SROM. For information about how to program an SROM, refer to your ROM programmer manual. After the SROM is programmed, it can be placed into the SROM socket on the motherboard. In addition, the mini-debugger is also available in the standard SROM provided with the Alpha microprocessor motherboards.
Hardware Debug Features 2.3 Hardware Debug Features The mini-debugger image is loaded into the CPU’s instruction cache at reset through the CPU’s SROM interface. The mini-debugger provides commands to: • Examine and deposit data in memory. • Test memory. • Examine and deposit internal CPU registers. • Load an image into the motherboard’s memory and transfer execution to it.
Setting Up the SROM Serial Port Connection Set terminal settings as shown in the following table: Terminal Setting Value Terminal emulation VT100 Transmit/receive speed 9600 baud Data bits 8 Parity None Stop bits 1 2.4.2 Connecting the Motherboard to a Personal Computer You can also use communication (terminal emulation) software running on a PC to communicate with the motherboard.
Setting Up the SROM Serial Port Connection All examples and command descriptions that follow assume that the motherboard SROM port is connected to COM1. 2.4.4 Connecting to the Motherboard from a System Running Windows NT Version 4.0 A system running the Windows NT version 4.0 operating system supports serial communication with the motherboard. Use the Start button on the taskbar to configure a COM port for connection to the motherboard and follow these steps: 1. Choose the Programs menu. 2.
Setting Up the SROM Serial Port Connection All examples and command descriptions that follow assume that the motherboard SROM port is connected to port /dev/tty00. To enable these ports for use with the motherboard, follow these steps: 1. Log in as superuser. 2. Modify the following two files: /etc/remote /etc/inittab a. Add the following two lines to the /etc/remote file. These lines define a device to connect to when using the DIGITAL UNIX tip command.
Starting and Running the Mini-Debugger 2.5 Starting and Running the Mini-Debugger After the SROM serial port connection has been made, you can initialize the mini-debugger by typing an ASCII character. This returns an SROM> prompt, which indicates that you are ready to begin debugging hardware and displays the minidebugger version number. For example: U V00000801 SROM> Once an ASCII character is typed, the mini-debugger automatically detects the baud rate of the terminal connected to the SROM serial port.
Sample Session on the EB64 2.6 Sample Session on the EB64 For the EB64 and the EB64+, the BIU_CTL register is cleared when you start the mini-debugger. Before any memory command can be executed on the EB64, the BIU_CTL register and the EB64 system register must be set to some meaningful value. Note: To avoid damaging your hardware, bit 2 (OE) of the BIU_CTL is set at power-on and whenever the BIU_CTL register is written (from the dc bctl command).
Sample Session on the EB64 2.6.1 EB64 Sample Log File The following sample log file initializes the EB64. ! Sample EB64 Initialization Log file. V00001c01 SROM> dc IPR> bctl D> e2000e444 *BCTL 0000000e.2000e444 SROM> ec Abox 00000000.00000000 Icsr 00000000.00bf0000 PalB 00000000.00000000 ExAd 00004000.00000002 DcSt 00000000.0000000f Hirr 00000000.00000000 Hier 00000000.00000000 BCtl 0000000e.2000e444 BiSt 00000000.00003240 BiAd 00000000.28210b88 Syn 00000000.00000000 FiAd 00000000.
Sample Session on the EB64 SROM> dm A> 7680 D> 0 SROM> dm A> 7600 D> 5 SROM> dm A> 7680 D> 400 SROM> dm A> 2180 D> 74000000 SROM>dm A> 2080 D> 1100 SROM> dm A> 2080 D> 0 SROM> ba 00000002.c0000000 BaseAddr OFF ! Disable use of base address. SROM> wa Wrt Addr ON ! Use destination address as data ! for any write operations. SROM> mt A> 0 A> 2000000 ! Perform memory test of entire 32MB. SROM> bm A> 100000 A> 100020 00000000.00100000: 00000000.00100004: 00000000.00100008: 00000000.0010000c: 00000000.
Sample Session on the EB64+ and the AlphaPC 64 2.7 Sample Session on the EB64+ and the AlphaPC 64 To run the mini-debugger on the EB64+ or the AlphaPC 64, set up the BIU_CTL register with the backup cache (Bcache) disabled. For example: BIU_CTL : 0000004E 4001E664 0000004E 4001E644 ! for EB64+ ! for AlphaPC 64. After main memory is initialized, the Bcache can be enabled as shown in the EB64+ sample log. The example assumes a system with a 2MB Bcache.
Sample Session on the EB64+ and the AlphaPC 64 3. Configure the Digital Semiconductor 21071-CA to use the Bcache tags, and set the BIU_CTL register in the Alpha 21064 to enable the Bcache. 4. Enable the Dcache. Before accessing the PCI bus on the EB64+, several registers in the Digital Semiconductor 21071-DA must be initialized. • The PCI Master Latency Timer must be set up before any PCI accesses are attempted.
Sample Session on the EB64+ and the AlphaPC 64 D> 2684 SROM> dm A> e00 D> c01 ! Init Bank 0 Timing Register B. SROM> dm A> 800 D> 0 ! Set Bank 0 Base Address Reg to 0. SROM> dm A> a00 D> eb ! Init Bank 0 Configuration Register ! to 32MB of memory. SROM> ba 00000001.80000000 BaseAddr OFF ! Disable use of base address. SROM> fm A> 0 A> 2000000 D> 0 ! Write good data and parity to all of ! memory. ! Total memory size = 32MB.
Sample Session on the EB64+ and the AlphaPC 64 A> 0 D> 1b4 ! Enable Bcache, ignore tag, and allocate ! on write operations. SROM> dm A> 60 D> 0 ! Clear the Tag Enable Register. SROM> ba 00000001.80000000 BaseAddr OFF SROM> fm A> 0 A> 200000 D> 0 SROM> ba 00000001.80000000 BaseAddr ON ! Write to entire cache to init cache ! tags and data. ! Set this to BCache size = 2MB. SROM> dm A> 60 D> 3fe0 ! Set Tag Enable Register to 2MB BCache. SROM> dm A> 0 D> b4 ! Clear the ignore tag bit previously set.
Sample Session on the EB66 and EB66+ ! The next section inits the PCI interface of the DC21071. SROM> dm A> 1a00001e0 D> ff ! Set PCI Master Latency Timer to 255. SROM> dm A> 1a00001c0 D> 0 ! Init HAXR2. SROM> em ! Perform a PCI configuration read of SIO. A> 1e0080000 00000001.e0080000: 04848086 SROM> wa Wrt Addr ON SROM> mt A> 0 A> 2000000 SROM> 2.8 Sample Session on the EB66 and EB66+ To run the mini-debugger on the EB66 or the EB66+, first determine the memory and Bcache size for your motherboard.
Sample Session on the EB66 and EB66+ 2. Set the Global Timing Register (GTR). For example, if you use 70-ns SIMMs, use the value from the following table, corresponding to your CPU speed: CPU Speed EB66 GTR Value EB66+ GTR Value 66 MHz 0x007C10A1 0x007C10A2 100 MHz 0x10BC1CE3 0x00BC1CC3 166 MHz 0x11343185 0x01343146 200 MHz 0x21743DE7 0x01743DA6 233 MHz 0x21AC4629 0x11B445C8 266 MHz 0x31EC528A 0x11EC5249 300 MHz 0x322C5EEB 0x122C5EBA 3. Initialize the Bcache.
Sample Session on the EB66 and EB66+ 5. Load the cache control register (CAR) to set the Bcache timing and size as well as to disable ECC and parity.
Sample Session on the EB66 and EB66+ The following table displays the BCR and BMR values for the selected bank size. Bank Size SIMM Type BCR BMR 8MB 1MB×36 44C0 700000 16MB 2MB×36 64C0 F00000 32MB 4MB×36 45C0 1F00000 64MB 8MB×36 65C0 3F00000 128MB 16MB×36 47C0 7F00000 In the EB66 sample log file shown in Section 2.8.1, there are two banks with 4MB×36 SIMMs for a total memory size of 64MB. 9. Write good parity and ECC to memory by writing all memory locations.
Sample Session on the EB66 and EB66+ SROM> dm A> 60 D> 11343185 ! ! ! ! Set Global Timing Register (GTR) with refresh enabled, bit [18] = 1. Based on 70 ns SIMMs and 166 MHz CPU. See table for other CPU speeds. ! Configure the memory banks for the fully supported memory size. SROM> dm A> 0 D> 43c0 ! ! BCR0. Ignores ECC bit. Bank Base 0x0. SROM> dm A> 8 D> 80043c0 ! ! BCR1. Ignores ECC bit. Bank Base 0x8000000. SROM> dm A> 10 D> 100043c0 ! ! BCR2. Ignores ECC bit. Bank Base 0x10000000.
Sample Session on the EB66 and EB66+ SROM> dm A> 48 D> 645521 ! ! Bank Timing 1. For EB66+ use 68933. SROM> dm A> 50 D> 645521 ! ! Bank Timing 2. For EB66+ use 68933. SROM> dm A> 58 D> 645521 ! ! Bank Timing 3. For EB66+ use 68933. SROM> ba 00000001.20000000 BaseAddr OFF ! Perform 8 consecutive RAS cycles to each memory bank to “wake up” the ! DRAMs. SROM> fm A> 0 A> 20000000 D> 0 ! ! ! ! ! ! Maximum memory size supported. ! This may take several seconds.
Sample Session on the EB66 and EB66+ SROM> ba 00000001.20000000 BaseAddr ON SROM> dm A> 78 D> 6b55 ! ! ! ! Enable ECC checking (bit 4) and tag parity (bit 2) in the Bcache. Same value as before but with these two bits set. ! Setting Bank Configuration Registers for 4MB x 36 SIMMs. ! Do this only for installed banks. SROM> dm A> 0 D> 45c0 SROM> dm A> 8 D> 20045c0 SROM> dm A> 10 D> 0 SROM> dm A> 18 D> 0 ! Setting Bank Mask Registers for 4MB x 36 SIMMs.
Sample Session on the EB164 SROM> fm A> 0 A> 4000000 D> 0 ! 64MB. ! Initialize the Error Status Register. SROM> ba 00000001.20000000 BaseAddr ON SROM> em A> 68 00000001.20000068: 00001003 SROM> dm A> 68 D> 1003 SROM> em A> 68 00000001.20000068: 00000000 ! Clear PCI RST signal to allow the PCI bus to run. SROM> dm A> 1800000c0 D> 0 SROM> dm A> 180000020 D> 0 ! Enable access to the PCI configuration registers. SROM> 2.
Sample Session on the EB164 To initialize the EB164, follow these steps: 1. Flush the secondary cache (L2) and turn on only one set. The reason to flush the secondary cache is to prevent any type of parity errors; only one set is turned on to facilitate read operations that need to go all the way out to memory and not be cached. 2. Turn off the Bcache to facilitate read operations that need to go all the way out to memory and not be cached.
Sample Session on the EB164 11. At this point, memory initialization is complete. If you want to perform I/O tests, then you need to initialize that part of the system and: a. Reset the ISA bus. b. Configure SIO, enabling accesses to RTC, configuration RAM configuration jumpers), and flash ROM space. 2.9.1 EB164 Sample Log File The following sample log file initializes the EB164. ! EB164 Log. ! ! ! ! Flush secondary cache, set block size to 64 bytes and turn on set S0 only to facilitate memory accesses.
Sample Session on the EB164 SROM> dm A> 8740000100 D> 2100c0f1 ! Set the CIA_CTRL register. SROM> dm ! Set the PCI timer register. A> 87400000C0 D> ff00 ! Set the CIA_CACK_EN register. Note that the ! Bcache victim bit has been set to 0 since the ! Bcache has been disabled. SROM> dm A> 8740000600 D> 0 SROM> sb A> 8750000000 00000087.50000000 BaseAddr ON ! Set base address for memory controller. SROM> dm A> 0 D> 1fe01 ! Set the refresh rate, Bcache size to 0 (disabled) ! and memory width to 256-bits.
Sample Session on the EB164 SROM> fm A> 0 > 4000000 D> 0 ! Total memory size. ! This may take a few seconds. ! Turn on the DCache. SROM> dc IPR> dcmd D> 1 *DCMD 00000000.00000001 ! Turn on the Bcache. SROM> dc IPR> bctl D> 8051 *BCTL 00000000.00008051 ! The BCFG value shown is for a 266MHz CPU, with 2MB, 10ns Bcache. ! For other configurations, use maximum read and write speeds allowed. SROM> dc IPR> bcfg D> 1e22772 *BCFG 00000000.01e22772 SROM> ec BCtl 00000000.00008051 BCfg 00000000.01e22772 ....
Sample Session on the EB164 SROM> fm A> 0 A> 4000000 D> 12345678 2–26 ! Fill memory to obtain good ECC. ! Total memory size in board. SROM> bm A> 0 A> 20 00000000.00000000: 00000000.00000004: 00000000.00000008: 00000000.0000000c: 00000000.00000010: 00000000.00000014: 00000000.00000018: 00000000.0000001c: 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 SROM> bm A> 200000 A> 200020 00000000.00200000: 00000000.00200004: 00000000.00200008: 00000000.0020000c: 00000000.
Sample Session on the EB164 SROM> sb A> 8700000000 00000087.00000000 BaseAddr ON ! Set base address for PCI configuration ! space. SROM> dm A> 809a0 D> 5800 ! Reset the ISA bus. ! Assert the reset signal. SROM> dm A> 809a0 D> 5000 ! Deassert the reset signal. SROM> dm A> 809c0 D> c30000 ! Set UBCSA register to allow access to ! RTC, keyboard, lbios and xbios. SROM> dm A> 809e0 D> ff000000 ! Set UBCSB register to allow access to ! configuration jumpers (address 0x801-2).
Sample Session on the AlphaPC 164 2.10 Sample Session on the AlphaPC 164 To run the mini-debugger as a standalone program on the AlphaPC 164, the following setup needs to be performed. The mini-debugger performs minimal initialization of the CPU and the user must initialize the rest of the board. To initialize the AlphaPC 164, follow these steps: 1. Flush the secondary cache (L2) and turn on only one set.
Sample Session on the AlphaPC 164 3. Initialize the CIA control register. 4. Initialize the CIA acknowledge register to disable the Bcache Victim Acknowledge signal. 5. Initialize the memory control register. This register controls the refresh rate and memory width. 6. Set the bank timing registers. AlphaPC 164 uses only one of these three registers. 7. Enter the appropriate values into the MBA registers, which control the only memory bank in AlphaPC 164.
Sample Session on the AlphaPC 164 Mask Row Type MBA Value [15:00] Wrap/Side 2 Addresses 16MB 00000 10×10 0001 0×100000 2 32MB 00000 10×10 0001 0×100000 /16MB 16MB 1 64MB 00011 11×11 0033 0×200 8M×36 32MB 2 128MB 00011 11×11 0033 0×200/64MB 16M×36 64MB 1 256MB 01111 12×12 00F5 0×100 32M×36 128MB 2 512MB 01111 12×12 00F5 0×100/256MB SIMM Density SIMM Size Sides 128-bit Memsize Mask Row Type MBA Value [15:00] Wrap/Side 2 Addresses 1M×36 4MB 1 32MB 00001
Sample Session on the AlphaPC 164 2.10.1 AlphaPC 164 Sample Log File The following sample log file initializes the AlphaPC 164. ! ! ! ! ! ! AlphaPC 164 Log. Flush secondary cache, set block size to 64 bytes and turn on set S0 only to facilitate memory memory accesses. Note that the secondary cache can’t be turned off completely. V00001c01 SROM> dm A> fffff000a8 D> 3002 SROM> em ! Check previous write operation. A> fffff000a8 000000ff.fff000a8: 00003002 SROM> dc IPR> bctl D> 8040 *BCTL 00000000.
Sample Session on the AlphaPC 164 SROM> ec BCtl 00000000.00008040 BCfg 00000000.01f21bb0 Icsr 000000c2.4e000000 PalB 00000000.00000000 ExAd 00000000.00000000 Ipl 00000000.0000001e Int 00000000.00000015 Isr 00000000.00200000 IcPE 00000000.00000000 DcMd 00000000.00000000 DcPE 00000000.00000000 ! Note changes to BCtl and BCfg. SROM> dm A> 8740000100 D> 2104c0f5 ! Set the CIA_CTRL register. SROM> dm ! Set the PCI timer register. A> 87400000C0 D> ff00 ! Set the CIA_CACK_EN register.
Sample Session on the AlphaPC 164 SROM> dm A> b40 D> 60208142 ! ! ! ! ! ! ! ! ! ! Set Bank Timing Register #1. In AlphaPC 164, all 8 memory address registers (MBAs) must be programmed. The first 4 cover side 0 of the SIMMs and the last 4, side 1 (if present). In this example all 8 SIMMs fully populated with 2Mbx36 SIMMs (8MBytes SIMMs) which gives a total of 64MBs. The first 4 MBA registers cover side 0, whose base address (bits 25:16) is 0.
Sample Session on the AlphaPC 164 SROM> dm A> 980 D> 20011 ! MBAE. SROM> ba 00000087.50000000 BaseAddr OFF ! Perform 8 consecutive RAS cycles to “wake up” memory. SROM> fm A> 0 A> 4000000 D> 0 SROM> dc IPR> dcmd D> 1 *DCMD 00000000.00000001 ! Total memory size. ! This may take a few seconds. ! Turn on the DCache. ! The BCFG and BCTL values shown are for a 366MHz CPU, with ! 1MB Bcache. For other configurations, see table. SROM> dc IPR> bcfg D> 1f21691 *BCFG 00000000.
Sample Session on the AlphaPC 164 SROM> ec BCtl 00000004.c4008051 BCfg 00000000.01f21691 Icsr 000000c2.4e000000 PalB 00000000.00000000 ExAd 284c8800.00080000 Ipl 00000000.0000000e Int 00000000.00000015 Isr 00000000.00200000 IcPE 00000000.00000000 DcMd 00000000.00000001 DcPE 00000000.00000000 ! Make sure changes are reflected here. SROM> dm A> 8740000600 D> 8 ! Enable CACK of Bcache Victims. SROM> dm A> fffff000a8 D> f000 ! Enable all 3 sets in the secondary cache ! and leave at 64-byte blocks.
Sample Session on the AlphaPC 164 SROM> mt A> 0 A> 4000000 ! Perform a memory test. SROM> wa Wrt Addr OFF SROM> sb A> 8700000000 00000087.00000000 BaseAddr ON ! Set base address for PCI configuration ! space. SROM> dm A> 809a0 D> 4800 ! Reset the ISA bus. ! Assert the reset signal. SROM> dm A> 809a0 D> 4000 ! Deassert the reset signal. SROM> dm A> 809c0 D> c00000 ! Set UBCSA register to allow access to ! lbios and xbios.
Sample Session on the AlphaPC 164 SROM> em ! Read first byte of flash. If it has an A> 86fff80000 ! image with the standard ROM header, you 00000086.fff80000:5a5ac3c3 ! will see this signature. ! Enable the Real Time Clock in the SMC chipset. SROM> dm A> 8580006e00 D> 55 ! Put SMC in configuration mode ! by writing to I/O address 0x370 ! the value 0x55 twice. SROM> dm A> 8580006e00 D> 55 SROM> dm A> 8580006e00 D> 20 ! Read the device ID and rev. SROM> em A> 8580006e20 00000085.
Sample Session on the AlphaPC 164LX SROM> dm A> 8580006e20 D> 0100 SROM> dm A> 8580006e00 D> AA ! Put SMC in run mode by writing ! 0xAA to address 0x370. ! The RTC is now ready to be used. 2.11 Sample Session on the AlphaPC 164LX To run the mini-debugger as a standalone program on the AlphaPC 164LX, the following setup needs to be performed. The mini-debugger performs minimal initialization of the CPU and the user must initialize the rest of the board.
Sample Session on the AlphaPC 164LX BBARQ-1 registers receive the base address bits [33:24] in bits [15:6]. BCR0-1 registers receive the bank size as in the following table: Bank Size Register Value 16MB 2C 32MB 2A 64MB 28 128MB 26 256MB 24 512MB 22 Each BCR register is first written with the appropriate value from the preceding table and then again with the low bit set to enable the banks. 5. Wake up memory by performing eight consecutive RAS cycles to each DIMM side.
Sample Session on the AlphaPC 164LX V00001f01 SROM> dm A> fffff000a8 D> 3002 ! SC_CTL register. SROM> em A> fffff000a8 000000ff.fff000a8:00003002 ! Check previous write operation. SROM> dc IPR> bctl D> 8040 *BCTL 00000000.00008040 ! Disable the Bcache and turn off ! error reporting. ! The read and write speeds in the Bcache Cfg register are set ! using the table based on the CPU speed. This example is for 466 MHz. SROM> dc IPR> bcfg D> 3f346a2 *BCFG 00000000.
Sample Session on the AlphaPC 164LX SROM> dm A> 8750000000 D> 3a1401 ! Set MCR (memory control register). SROM> dm A> 8750000300 D> 750 ! Set RTR again to force a ! refresh after the MCR has been set. ! Set the memory bank registers for two banks of DIMMs totalling ! 128MB. SROM> dm A> 8750000600 D> 0 ! Set memory BBAR0 ! (base address register 0). SROM> dm A> 8750000640 D> 100 ! Set memory BBAR1. SROM> dm A> 8750000a00 D> 22 ! Set memory BTR0 ! (base timing register 0).
Sample Session on the AlphaPC 164LX SROM> fm A> 0 A> 8000000 D> 0 SROM> dc IPR> dcmd D> 1 *DCMD 00000000.00000001 ! Fill 128MB with zeros. ! Turn on the DCache. ! Set BCFG and BCTL for 466 MHz CPU with 2MB Bcache. 2–42 SROM> dc IPR> bcfg D> 3f346a2 *BCFG 00000000.03f346a2 ! Set CPU BC_CONFIG register. SROM> dc IPR> bctl D> c4008051 *BCTL 00000000.c4008051 ! Set CPU BC_CONTROL register. SROM> ec BCtl 00000000.c4008051 BCfg 00000000.03f346a2 Icsr 000000c2.4e000000 PalB 00000000.
Sample Session on the AlphaPC 164LX ! Clear any possible errors in the CPU and memory controller. ! SC_STAT register. SROM> em A> fffff000e8 000000ff.fff000e8: 00000000 ! EI_STAT register. SROM> em A> fffff00168 000000ff.fff00168: e5ffffff SROM> dm A> 8740008200 D> 1 ! PYXIS_ERR. ! Writing 1 clears any errors. SROM> wa Wrt Addr ON SROM> mt A> 0 A> 8000000 SROM> wa Wrt Addr OFF SROM> sb A> 8700000000 00000087.00000000 BaseAddr ON ! Set base address for PCI configuration ! space.
Sample Session on the AlphaPC 164LX SROM> dm A> 809e0 D> ff000000 ! Set UBCSB register to allow access ! to configuration jumpers ! (address 0x801-2). SROM> em A> 80000 00000087.00080000:04848086 ! Read SIO identification registers. ! The value shown is the Intel ID for ! this part. SROM> ba 00000087.00000000 BaseAddr OFF SROM> dm A> 8580001000 D> f0 ! Write out to the LEDs post-card. You ! should see an “F0” on it. SROM> em A> 86fff80000 00000086.fff80000:5a5ac3c3 ! Read first byte of flash.
Onboard Machine Check Handler SROM> dm A> 8580006e20 D> 0600 ! RTC. SROM> dm A> 8580006e00 D> 70 ! Select the interrupt register. SROM> dm A> 8580006e20 D> 0800 ! Configure to interrupt as IRQ8. SROM> dm A> 8580006e00 D> 30 ! Activate the RTC. SROM> dm A> 8580006e20 D> 0100 SROM> dm A> 8580006e00 D> AA ! Put SMC in run mode by writing ! 0xAA to address 0x370. ! The RTC is now ready to be used. 2.
Onboard Machine Check Handler Syn FiAd SROM> 2–46 Getting Started 00000000.00000000 00000000.
3 SROM Mini-Debugger Command Set 3.1 Overview This chapter describes the Alpha Microprocessors SROM Mini-Debugger command set. 3.2 Command and User Interface Features The following list describes some of the features of the mini-debugger command language: • Uppercase or lowercase characters can be used interchangeably. • Only the first two characters of a command line are significant; the rest are ignored. • Numbers are input and output in hexadecimal format.
Command Summary • All stores are followed with two MB instructions. This keeps writes ordered (from the system’s point of view) and prevents merging in the write queue. For more information on the MB instruction, see the CPU’s hardware reference manual. • For commands that use an address range, the ending address is not included in the range. The last read or store is performed in the immediately preceding quadword or longword, depending on the state of the qw data flag. 3.
User Commands Table 3–1 Command Summary Command (Sheet 2 of 2) Description Deposit/Examine Commands dc Deposit internal CPU register. dm Deposit data to memory location. ec Examine internal CPU registers. em Examine data in a memory location. Print Commands fl Print current state of flags. pr Print contents of general purpose cpu registers. Load/Execute Commands rt Exit minidebugger. st Start executing at specified address. xb Begin execution of the last image loaded.
User Commands !d The negate data (!d) command enables or disables the use of the one’s complement of the data to be written by toggling the negate data flag. Control Flags Not applicable. Description When the negate data flag is enabled, writes will use the complement (negation) of the data specified by the user or automatically generated by the command in use. The default state is off.
User Commands SROM> bm A> 600000 A> 600020 00000000.00600000: 00000000.00600004: 00000000.00600008: 00000000.0060000c: 00000000.00600010: 00000000.00600014: 00000000.00600018: 00000000.0060001c: 0000ffff ffff0000 0000ffff ffff0000 0000ffff ffff0000 0000ffff ffff0000 If the write address flag is also enabled, then data written is the complement of the destination address. SROM> wa Wrt Addr ON SROM> fm A> 500000 A> 500010 SROM> bm A> 500000 A> 500010 00000000.00500000: 00000000.00500004: 00000000.
User Commands ba The base address flag (ba) command enables or disables the use of the base address set with the set base (sb) command. It does this by toggling the base address flag. Control Flags Not applicable. Description When the base address flag is enabled, the address entered with the sb command is added to addresses entered in any subsequent examine or deposit command. The default state is off. Example To access addresses in the following range, 3.FFF80000 to 3.
User Commands SROM> ba 0000003.fff80000 BaseAddr ON SROM> bm A> 30 A> 40 00000003.fff80030: 00000003.fff80034: 00000003.fff80038: 00000003.
User Commands bm The block memory (bm) command displays the data read from a specified range of addresses. Control Flags ba (base address flag) di (display flag) fr (follow-with-read flag) fw (follow-with-write flag) lo (loop flag) qw (quadword data flag) Description The block memory command reads data from a block of memory locations and prints it out to the screen if the display flag is enabled. The range is specified by first entering the starting address, followed by the ending address.
User Commands cm The compare (cm) command compares two sections of memory and displays any differences. Control Flags ba (base address flag) lo (loop flag) qw (quadword data flag) Description The compare command checks the equality of two blocks of memory and prints any differences. The first two addresses specify the starting and ending addresses of the first block to be checked and the third input provides the starting address of the second block.
User Commands 3–10 SROM> di Disp OFF ! Does not affect the compare command. SROM> cm A> 500000 A> 500020 A> 600000 00000000.00500004: 00000000.00600004: 00000000.0050000c: 00000000.0060000c: ! Compare both sections.
User Commands cp The copy (cp) command reads data from a range of addresses and writes it to another. Control Flags ba (base address flag) lo (loop flag) qw (quadword data flag) Description The copy command moves sections of data from one place in memory to another. The first two addresses specify the starting and ending addresses of the block to be moved. The third input provides the destination address for the copy.
User Commands dc The deposit CPU register (dc) command changes the contents of internal CPU registers. Control Flags Not applicable. Description The deposit CPU register command changes the contents of internal CPU registers. These registers are CPU dependent, so command input is different for each Alpha CPU. The following tables show the names assigned by the mini-debugger to the CPU registers; these are the only valid names that may be entered at the IPR prompt.
User Commands Table 3–2 CPU Register Names for the dc Command Mini-debugger Name CPU Register Name (Sheet 2 of 2) Description 21066 Abox* ABOX_CTL Abox control Icsr ICSR Ibox control and status PalB PAL_BASE PAL base address * Write-only registers whose values are obtained from a copy placed in PALtemp registers 1and 2 when they were written with the dc command.
User Commands di The display (di) command enables or disables the display of data to the screen by toggling the display flag. Control Flags Not applicable. Description When the display flag is enabled, the examine commands print the data obtained. When it is disabled, the read operations still take place but the data is not displayed. The cm and mt commands, which produce read operations of their own, ignore the state of this flag and always display the data if there is a mismatch.
User Commands The next example shows that the cm command is not affected by this flag’s state and prints out data whenever a mismatch occurs. SROM> di Disp OFF SROM> cm A> 500000 A> 500010 A> 600000 00000000.00500000: 00000000.00600000: 00000000.00500004: 00000000.00600004: 00000000.00500008: 00000000.00600008: 00000000.0050000c: 00000000.
User Commands dm The deposit memory (dm) command writes a data pattern to one memory location. Control Flags !d (negate data flag) ba (base address flag) fr (follow-with-read flag) fw (follow-with-write flag) lo (loop flag) qw (quadword data flag) wa (write address flag) Description The deposit memory command writes a data pattern to the specified memory location. If the quadword flag is enabled, then 64 bits of data are written; otherwise, only 32 bits of data are used.
User Commands SROM> em ! Examine contents of address 500000 A> 500000 00000000.00500000: 89abcdef 00000000.00500000: 89abcdef 00000000.
User Commands ec The examine CPU registers (ec) command prints the contents of internal CPU registers. Control Flags Not applicable. Description The examine CPU registers command displays the contents of internal CPU registers. These registers are CPU dependent, so command output is different for each Alpha CPU.
User Commands Table 3–3 CPU Register Names for the ec Command Mini-debugger Name CPU Register Name (Sheet 2 of 2) Description DS21064 Abox* ABOX_CTL Abox control Icsr ICSR Ibox control and status PalB PAL_BASE PAL base address ExAd EXC_ADDR Exception address DcSt DC_STAT Data cache status Hirr HIRR Hardware interrupt request Hier HIER Hardware interrupt enable BCtl* BC_CONTROL Bcache control BiSt BIU_STAT Bus interface unit status BiAd BIU_ADDR Bus interface unit address
User Commands Example The following example shows the output of an ec command on a DS21064 CPU: SROM> ec Abox 00000000.00000002 Icsr 00000000.00ff0000 PalB 00000000.00000000 ExAd 00000000.00200cb4 DcSt 00000000.0000000b Hirr 00000000.00000000 Hier 00000000.00001890 BCtl 000007f8.00000000 BiSt 00000000.000010c1 BiAd 00000001.e0000018 Syn 00000000.00000000 FiAd 00000000.
User Commands em The examine memory (em) command reads data from one memory location. Control Flags !d (negate data flag) ba (base address flag) di (display flag) fr (follow-with-read flag) fw (follow-with-write flag) lo (loop flag) qw (quadword data flag) Description The examine memory command reads data from the specified memory location and displays it on the screen if the display (di) flag is enabled. Depending on the state of the quadword data flag, 32 or 64 bits will be displayed.
User Commands fl The flags (fl) command displays the current state of all flags. Control Flags Not applicable. Description The behavior of many of the mini-debugger commands can be affected by the state of one or more of eight available flags. The flags command displays on the screen the current state of these flags. Example In the following example, the default state of all flags, except the display flag, is off (disabled). Their states can be changed by issuing the appropriate command.
User Commands SROM> fl FollowWr FollowRd BaseAddr Neg Data Wrt Addr Loop OFF Disp ON QW OFF OFF OFF OFF ON ON SROM Mini-Debugger Command Set 3–23
User Commands fm The fill memory (fm) command writes data to the specified range of addresses. Control Flags !d (negate data flag) ba (base address flag) fr (follow-with-read flag) fw (follow-with-write flag) lo (loop flag) qw (quadword data flag) wa (write address flag) Description The fill memory command writes to a range or block of memory locations. The range is specified by first entering the starting address, followed by the ending address.
User Commands SROM> bm A> 3ffff7 A> 40005f 00000000.003ffff0: 00000000.003ffff8: 00000000.00400000: 00000000.00400008: 00000000.00400010: 00000000.00400018: 00000000.00400020: 00000000.00400028: 00000000.00400030: 00000000.00400040: 00000000.00400048: 00000000.00400050: fff0ffff.fff0ff7d fff0ffff.fff0ffff 01234567.89abcdef 01234567.89abcdef 01234567.89abcdef 01234567.89abcdef 01234567.89abcdef 01234567.89abcdef 01234567.89abcdef 01234567.89abcdef 00000000.00000000 00000000.
User Commands SROM> !d Neg Data ON SROM> fm A> 400000 A> 400020 D> 0 SROM> bm A> 400000 A> 400020 00000000.00400000: 00000000.00400004: 00000000.00400008: 00000000.0040000c: 00000000.00400010: 00000000.00400014: 00000000.00400018: 00000000.
User Commands fr The follow-with-read (fr) command toggles the follow-with-read flag, enabling or disabling the execution of a read operation after the last operation executed by a command.
User Commands For example, writing to address 0x600000 and reading from 0x800000 ejects the cached write of address 0x600000. From the system memory’s point of view, a read of 0x800000 will be followed with a write of 0x600000, followed by another read of 0x800000 and so on until the loop is broken by pressing a key. SROM> lo Loop ON ! Repeat command until a key is pressed. SROM> fr FollowRd ON ! Follow deposit command with a read. SROM> di Disp OFF ! Don’t display the data from the read.
User Commands SROM> fm A> 600000 A> 600020 A> 600000 00000000.00600000: 00000000.00600004: 00000000.00600008: 00000000.0060000c: 00000000.00600010: 00000000.00600014: 00000000.00600018: 00000000.0060001c: ! Starting address of fill memory command. ! Ending address of fill memory command. ! Address to begin reading from.
User Commands SROM> fw FollowWr ON ! Follow with a write (before the read). SROM> fr FollowRd ON ! Follow deposit command with a read. SROM> fm A> 500000 A> 500020 A> 600000 00000000.00500000: 00000000.00500004: 00000000.00500008: 00000000.0050000c: 00000000.00500010: 00000000.00500014: 00000000.00500018: 00000000.0050001c: 3–30 ! Begin to write at this address ! and end with this one. ! Write to this address range after each ! write from first block. 00500000 ! Reads from first block.
User Commands fw The follow-with-write (fw) command toggles the follow-with-write flag, enabling or disabling the execution of a write operation after the last operation executed by a command. Control Flags Not applicable.
User Commands SROM> fm A> 400000 A> 400010 A> 500000 D> abcdef ! First block gets written with data pattern. ! Second block also gets written with the same data pattern. SROM> bm A> 500000 ! Read from this block. A> 500010 A> 600000 ! Write to this block. 00000000.00500000: 00abcdef 00000000.00500004: 00abcdef 00000000.00500008: 00abcdef 00000000.0050000c: 00abcdef SROM> fw FollowWr OFF SROM> bm ! This shows that a copy function has taken place. A> 600000 A> 600010 00000000.00600000: 00abcdef 00000000.
User Commands lo The loop (lo) command enables or disables looping or repeating of a command by toggling the loop flag. Control Flags Not applicable. Description When the loop flag is enabled, examine and deposit commands are repeated until you stop the looping by pressing a key. This feature is useful for hardware timing of read and write operations to the external cache or memory system, or anytime a command needs to be repeated continuously. The default state is off.
User Commands SROM> em A> 500000 00000000.00500000: 00000000.00500000: 00000000.00500000: 00000000.00500000: 00000000.00500000: 00000000.00500000: 00000000.00500000: 00000000.00500000: 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 ! (key pressed) The mt command continuously checks the range between 400000 and 500000.
User Commands mt The memory test (mt) command performs a simple write-read-compare test. Control Flags !d (negate data flag) ba (base address flag) fr (follow-with-read flag) fw (follow-with-write flag) lo (loop flag) qw (quadword data flag) wa (write address flag) Description The memory test command first writes to the memory range specified with the user-specified data or command-generated data. It then begins reading back the data and comparing it against what was written.
User Commands SROM> mt A> 400000 A> 500000 00000000.00400000:10400000 Expect: 00400000 00000000.00400004:10400004 Expect: 00400004 00000000.00400008:10400008 Expect: 00400008 00000000.0040000c:1040000c Expect: 0040000c 00000000.00400010:10400010 Expect: 00400010 00000000.00400014:10400014 Expect: 00400014 ! The data read back has an extra bit set.
User Commands pr The print register (pr) command displays the contents of the general-purpose CPU registers. Control Flags Not applicable. Description The contents of the general-purpose CPU registers are saved to PALtemp registers when the mini-debugger is first entered. The pr command allows for their viewing. Note that because the dc command uses two of these PALtemp registers, the results in R1 and R2 will be changed after a dc command.
User Commands Example SROM> pr R00: 00000000.00000000 R01: 00000000.00000006 R02: 000007f8.00000000 R03: 00000000.00000030 R04: 00000000.00000000 R05: 00000000.00000000 R06: 00000000.00300000 R07: 00000000.00001428 R08: 00000000.02000000 R09: 00000000.00000004 R10: 00000000.00026890 R11: 00000000.000262a0 R12: 00000000.00026560 R13: 0000004e.2001c665 R14: 00000000.00026590 R15: 00000000.000265a0 R16: 00000000.00026580 R17: 00000000.00008000 R18: 00000080.00000080 R19: 00000000.01ffdf30 R20: ffffffff.
User Commands qw The quadword (qw) command enables or disables the quadword data flag. Control Flags Not applicable. Description The quadword command changes the state of the quadword data flag. When the quadword data flag is enabled, all operations are performed on 64-bit data. When off, only 32 bits of data are used. The default state is off. Example In this example, the first bm command loads 32 bits of data using the ldl/p instruction from addresses 3.FFF80000, 3.FFF80004, 3.FFF80008, and 3.
User Commands rt The return (rt) command exits the mini-debugger. Control Flags Not applicable. Description The return command exits the mini-debugger, returning to the calling program if there is one. For the standalone mini-debugger, it simply exits. Returning from a mini-debugger built into the SROMs provided with the motherboards allows you to continue with the booting process, as if the minidebugger had not been invoked. The rt command is also useful during debugging of SROM code you may write.
User Commands sb The set base (sb) command defines the base address to be added to user-specified addresses when the base flag is enabled. Control Flags Not applicable. Description Using a base address is convenient when examining or depositing of the same address frame is needed (particularly when the high-order bits of the address must be set). The base address entered with the set base command is added to the addresses entered in any subsequent examine or deposit commands, saving the user some typing.
User Commands SROM> em A> 400000 00000000.00400000: 00400000 SROM> ba 00000003.fff80000 BaseAddr ON SROM> bm A> 30 A> 40 00000003.fff80030: 00000003.fff80034: 00000003.fff80038: 00000003.
User Commands st The start image (st) command begins execution at a specified address. Control Flags Not applicable. Description The start image command transfers control to the code residing at the specified address. If the address does not contain executable code, then the machine hangs. You must recycle the power to start again. Note: The Alpha Microprocessors SROM Mini-Debugger is stored in the instruction cache (Icache).
User Commands wa The write address (wa) command enables or disables the write address flag. Control Flags !d (negate data flag) Description When the write address flag is enabled, write operations use the destination address as their data. This allows for unique values to be written to individual locations (a useful feature when debugging the memory subsystem). If the negate data flag is enabled, the one’s complement of the address being written is used instead.
User Commands SROM> bm A> 400000 A> 400020 00000000.00400000: 00000000.00400004: 00000000.00400008: 00000000.0040000c: 00000000.00400010: 00000000.00400014: 00000000.00400018: 00000000.0040001c: 00400000 00400004 00400008 0040000c 00400010 00400014 00400018 0040001c SROM> qw QW ON SROM> fm A> 800000 A> 800030 SROM> bm A> 800000 A> 800030 00000000.00800000: 00000000.00800008: 00000000.00800010: 00000000.00800018: 00000000.00800020: 00000000.00800000 00000000.00800008 00000000.00800010 00000000.
User Commands SROM> bm A> 500000 A> 500020 00000000.00500000: 00000000.00500004: 00000000.00500008: 00000000.0050000c: 00000000.00500010: 00000000.00500014: 00000000.00500018: 00000000.
User Commands xb The external boot (xb) command begins execution of uploaded image. Control Flags Not applicable. Description The external boot command is used after an image has been uploaded with the xm command. It adds the necessary Icache flush code before it transfers control to the code residing at the address specified in the xm command. If no xm command has been executed, then this command has no effect.
User Commands xm The external image to memory (xm) command loads an image into memory. Control Flags Not applicable. Description The external image to memory command loads an external image into memory. The first input is the destination address, followed by the number of bytes to load. The number of bytes should be a multiple of 8 and the starting address should be quadword aligned. Normally, this command is used by an external utility called xload.
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Digital Semiconductor Products To order Alpha microprocessors and motherboards, contact your local distributor. The following tables list some of the semiconductor products available from Digital Semiconductor. Chips Order Number Alpha 21164-600 Microprocessor 21164–MB Alpha 21164-533 Microprocessor 21164–P8 Alpha 21164-466 Microprocessor 21164–IB Motherboard kits include the motherboard and motherboard user’s manual.
Title Order Number Digital Semiconductor AlphaPC 164LX Motherboard Technical Reference Manual EC–R46WA–TE Digital Semiconductor AlphaPC 164 Motherboard Product Brief EC–QUQKC–TE AlphaPC 164 Motherboard User’s Manual EC–QPG0B–TE Digital Semiconductor AlphaPC 164 Motherboard Technical Reference EC–QPFYB–TE Manual Digital Semiconductor AlphaPC 164 Motherboard Design Kit Read Me First EC–QPFZA–TE Digital Semiconductor AlphaPC 164 DIGITAL UNIX Product Brief EC–QZT6B–TE AlphaPC 164 Motherboard DIGITAL
Index A ABOX_CTL default setting, 2–6 AlphaPC 64 sample session, 2–10 Audience, vii B ba See base flag command base flag command, 3–6 Baud rate, 2–6 BIU_CTL register, 2–7 block memory command, 3–8 bm See block memory command boot, 2–5 C cm See compare command Command features, 3–1 Command summary, 3–2 Commands, 3–1 base flag, 3–6 block memory, 3–8 compare, 3–9 copy, 3–11 deposit CPU register, 3–12 deposit memory, 3–16 display, 3–14 examine CPU registers, 3–18 examine memory, 3–21 external boot, 3–47 extern
copy command, 3–11 cp See copy command D !d See negate data command EB66+ sample session, 2–14 ec See examine CPU registers command em See examine memory command examine CPU registers command, 3–18 dc examine memory command, 3–21 See deposit CPU register command Debugging memory faults, 2–45 external boot command, 3–47 external image to memory command, 3–48 Default conditions, 2–6 deposit CPU register command, 3–12 F deposit memory command, 3–16 Features, 1–1 command language, 3–1 hardware debug, 2
L S lo Sample session AlphaPC 164, 2–28 AlphaPC 64, 2–10 EB164, 2–21 EB64, 2–7 EB64+, 2–10 EB66, 2–14 EB66+, 2–14 sb See set base command Serial port connecting to, 2–5 Serial port setup, 2–2 See loop command load, 2–5 loop command, 3–33 M Machine check handler, 2–45 MCHK See machine check handler memory test command, 3–35 mt See memory test command set base command, 3–41 N Setting BIU_CTL register, 2–7 negate data command, 3–4 SROM serial port, 2–2 st O onnecting, 2–4 See start image command sta
Windows NT 4.0, 2–4 Windows NT 4.
