Technical data

BIOS and System Programming
74 VIPA GmbH CP486 ⋅ 00/14
Configuration Register (Address 0C9F82H)
The configuration register is used to configure the number of banks, bank size and mode of the bank
operation. Programming of this register approves the bank inerface for implementation towards PLC
side.
Assignment:
Bit76543210
L2 L1 L0 CP Lin K2 K1 K0
bank length
000 64KByte
001 16Byte
010 32Byte
011 64Byte
100 128Byte
101 256Byte
110 1KByte
111 8KByte
bank-operated
0 0 linear, no bank addressing
0 1 bank-operated via upper bank address
1 0 CP bank-operated via address D7DFEH
1 1 not allowed
number of banks
0 0 0 1 bank
0 0 1 2 banks
0 1 1 4 banks
1 1 1 8 banks
Annotation: The maximal RAM-size on the CP486 amounts to 8KByte.
For linear operation the number of banks must be set to 1.
Reset Interrupt Register (Address 0C9F8EH)
An PLC access to the last bank byte (in the case of 1KByte bank size at element 1023) triggers the
hardware interrupt 12 (software interrupt 74) at the CP486. The appropriate vector is filed in the
addresses 1D0-1D3. Concerning the operating mode bank operation via highest bank address it has
to be noted that bit 7 of the written date must have the value 1in order to address the bank byte (see
also section 4.3.8.1)
The interrupt has to be reset in the corresponding interrupt service routine by a write access to the
interrupt reset register (address C800:1F8E (hex)). The interrupt is automatically reset in the case of
a hardware reset.