Specifications

Multi Slave Product Re£erence Manual
Section 2
110 ADDRESS HAP
Each Multi Slave CPU has an identical I/O address map.
assignDents are as £ollowa:
ADDRESS (Hex) TYPE
FUNCTION
The port
OO-OF
R/W
DUART Data/Control (see Signetics
2681 Docu~entation £or details)
10-lF
Not Used
20-2F
R
Asserts SLAVE MESSAGE bit
30-3F
R De-asserts MASTER MESSAGE bit
40-4F
w BANK/PROM SELECT (details £ollow)
50-SF
R
STATUS PORT (MASTER and SLAVE bits)
60-6F
R
Asserts SLAVE ALIVER bit
70-7F
R/W
S-100 DATA PORT
Table 2-2 110 Port Aaaignaonta
The user should be aware that although it would appear that the
5-100 data ports would collide with one another, they are actual-
ly physically separated in the hardware. This is explained a bit
more clearly by the £ollowing diagram:
SLAVE PROCESSOR NUMBER MASTER PROCESSOR
#0 I/O ADDRESS 70H •••.••••••••.••.•..• I/0 BASE ADDRESS + 0
#1 1/0 ADDRESS 70H ••••••••••••.••..••• I/0 BASE ADDRESS + 4
#2 1/0 ADDRESS 70H •••••••••••••••••••• I/0 BASE ADDRESS + 8
SLAVE STATUS PORT (read by the Slave, read only>
+--+--+--+--+--+--+--+--+
1071061051041D31021011001
+--+--+--+--+--+--+--+--+
1----- 1 = MASTER message active
--------- 1 = SLAVE message active
Figure 2-5 SlavQ Status Port Bit Definitions
SLAVE 1/0 ADDRESS MAP Page 2-9