Specifications
Multi
Slave
Product
Re£erence
Manual
'::;ect.
i
OTl
:z
MASTER/SLAVE
COM~UNICAT!ONS
For
the
master
processor
to
send
data
to
the
slRve,
the
sl~v~
must
be
reading
the
5-100
data
port.
Conversly,
£or
the
slave
to
send
data
to
the
master,
the
slave
must
write
to
the
5-100
data
port
be£ore
the
master
reads
it.
As
mentioned
ea1'li~r,
when
the
slave
is
reading
or
writing
to
the
S-100
data
port,
it
is
placed
in
8 HOLD
(wait)
condition,
and
released
to
resume
processing
when
the
Master
Processor
writes
or
reads
the
corresponding
port.
This
ensures
that
the
master
and
slave(s)
remain
in
synchroniza-
tion
during
bus
communication;
reliable
network
operation
1s
achieved
when
the
other
status
bits
(ALIVE-,
READ/WRITE-,
and
HOLD-)
are
implemented
as
part
o£
a
communications
protocol.
The
Haster
Processor
may
reset
a
slave
processor
at
any
time
by
issuing
an
output
to
the
appropriate
slave
status
port
with
bit
D4
set.
To
reactivate
the
slave,
the
master
must
again
issue
an
output
byte
to
the
slave's
status
port
with
bit
D4
reset,
£01-
lowed
by
a
short
post-reset
delay.
An
e~arnple
of
this
sequence
is
shown
below:
SL_RES:
LD
A,lOH
SET
BIT
D4
OUT
(SLVBASE),A
;
OUTPUT
TO
SLAVE
BASE ADDRESS
LD
B,,16
;
LEAVE THE
BIT
SET
...
SL_R05:
DJNZ
SL
R05
. . .
FOR A
SHORT
TIME
)COR
NOT
10H
;
TURN OFF
BIT
D4
OUT
(SLVBASE),A
;
UN-RESET
THE SLAVE
LD
B,16
.
SET
UP
FOR
POST-RESET
DELAY ,
SL_R10:
EX
(SP),HL
;
THIS
IS
A
EX
(SP),HL
;
VERY
EFFECTIVE
DJNZ
SL
R10
;
TIME
WASTER
RET
;
RETURN
TO
CALLER
The
suggested
handshake
mechanism
between
the
master
and
slave
is
as
£ollows
(£or
transmission
£rom
slave
to
master):
the
slave
first
asserts
the
SLAVE MESSAGE
bit.
The
master
t,ay
see
this
by
polling
(reading
the
slave
status
pbrt),
or
the
Multi
Slave
may
be
configured
to
cause
an
interrupt
on
the
master.
In
either
case,
once
the
SLAVE MESSAGE
bit
has
been
asserted,
the
slave
CPU
then
outputs
its
£irst
data
byte
to
the
S-100
bus
communications
port.
Upon
doing
so,
the
slave
CPU
is
£orced
into
a
wait
condi-
tion,
which
the
master
must
veri£y
by
testing
the
WRITE-
and
HOLD~
bits
at
the
slave
status
port.
Once
the
master
has
deter-
mined
that
both
signals
are
true,
it
may
then
read
the
byte
waiting
at
the
S-100
data
port.
The
elave
is
rel~ased
to
resume
processing,
£ree
to
continue
sending
subsequent
data
bytes,
etc.
In
a
MASTER
Upon
master
to
slave
transmission,
the
master
must
SBsert
th8
bit,
which
the
slave
sees
by
polling
its'
status
port.
detecting
the
active
MASTER
bit,
the
elave
must
reset
it
MASTER/SLAVE
COMMUNICATIONS
o
'"'
- c;
..
age
.~
_