Specifications
Multi
Sleve
Product
Reference
Manual
Section
1
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PROM
.1
Z80-H
CPU
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Bank
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(1
of
3)
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Control
64k
& Timing
RAM
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NTER-
S-100
FACE
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BUS
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Figura
1-1
Mult!
Slave
Block
D1agraa
FUNCTIONAL
FLOW
Figure
1-1
illustrates
the
maJor
£unctionsl
components
of
the
Multi
Slave
computer
board.
Initially.
immediately
following
the
power-on/reset
event,
all
three
processors
are
held
in
a
reset
state.
Each
processor
must
be
individually
activated
by
e
net-
work
master.
Once
t.he
master
has
activated
a
Multi
Slave
pro-
cessor~
the
selected
slave
CPU
then
begins
executing
the
instruc-
tions
provided
by
the
onboard
EPROM.
Depending
upon
user
response
and
intervention,
the
proceenor
will
either
initiate
the
execu-
tion
of
the
resident
Monitor/Debug
program,
or
begin
the
download
request
sequence
to
receive
an
operating
system.
MAJOR
FUNCTIONAL
FLOW
Page
1-4