Service manual

90 Self-Tests
Target
Status
Code Status Description
68 Error: Selected target did not set any phase before releasing bus
70 Error: Target not following expected phase sequence
72 Error: Parity error detected during programmed I/O transfer
80 Error: Unexpected interrupt at start of DMA test
90 Error: Target failed to set command phase
92 Error: Unexpected interrupt at start of command phase sequence
94 Error: Timeout waiting for DMA complete in command phase in
DMA test
96 Error: No status<DMAEND> following command phase in DMA
test
98 Error: Wrong interrupt following command in DMA test
9A Error: scd_cnt not zero following command in DMA test
9C Error: DMA not complete after EOP in command phase (ACK
not clear soon enough)
A0 Error: Status<dmaend> bit not cleared by clearing mode<dma>
at start of data_in phase in DMA test
A2 Error: Target failed to set data_in phase in DMA test
A4 Error: Timeout waiting for DMA complete in data_in phase in
DMA test
A6 Error: No status<dmaend> following data_in phase in DMA test
A8 Error: Wrong interrupt following data_in phase in DMA test
AA Error: scd_cnt not zero following data_in phase in DMA test
AC Error: DMA not complete after EOP in data_in phase (ACK not
clear soon enough)
B0 Error: Status<dmaend>not cleared by clearing mode <dma> at
start of status phase in DMA test
B2 Error: Target failed to set status phase in DMA test
B4 Error: Timeout waiting for DMA complete in status phase in
DMA test
B6 Error: No status<dmaend> following status phase in DMA test