Technical data

Graphics Controller, Continued
Table 1–6 Diagnostic ROM/Configuration Register Bit Definitions
Bit Name Definition
<31> Scanproc Test This bit is driven by the Scanproc chip during
diagnostics.
<30> Time Out This bit is set when 2 VRAM refresh pulses
occur while DS is low, indicating a hung system.
<29:18> Reserved Read as zero.
<17> MSB This bit indicates the speed of the oscillator used
as timing for the 1280 X 1024 monitor. A zero
indicates 66 Hz operation, a one indicates 72 Hz
operation.
<16> Reserved Read as zero.
<15:0> ROM Data Field These bits contain the ROM data that represents
the diagnostic code for the video subsystem.
SPXg/gt
The SPXg and SPXgt modules were originally designed to be
installed into an LCG frame buffer connector on the Model 60
system. The DC7201 chip in the Model 60 system provided the
interface to the SPXg/gt graphics module. The DC7201 chip
provided a direct path for the processor to read and write SPXg/gt
registers along with support for DMA into the SPXg/gt FIFO. In
the Model 90 system, no DMA support for SPXg/gt is provided.
The SPXg/gt is accessible using three separate address ranges.
The base address range for SPXg/gt module is 2800.0000 to
29FF.FFFF. In addition, a direct access path to the Brooktree
RAMDAC is supported at addresses 2A00.0000 to 2A00.003C.
Finally the SPXg/gt diagnostic ROM is located at addresses
2A10.0000 to 2A17.FFFF. The diagnostic ROM is accessible a
word at a time on aligned quadword boundaries.
1–27