Technical data

Self-Test Descriptions, Continued
The following tests are included:
Register test
Verifies that the 53C94A Controller Chip registers are fully
functional. All read/write bits that can be written are written
to. It also verifies the bits.
Interrupt test
Verifies the SCSI bits in the interrupt mask register,
interrupt request register, and the interrupt clear register. A
SCSI interrupt is forced, with the SCSI bit in the interrupt
mask first set and then cleared. This is repeated for both a
high interrupt priority level and a low priority level.
Data Transfer test
Verifies SCSI bus communication between the controller
and the available peripherals and also the data path of
the controller to the memory. A series of four inquiry
commands are issued to each device. The commands are
issued in the programmed I/O mode, asynchronous mode
with DMA, asynchronous mode with the DMA starting on a
non-word-aligned boundary and crossing a page boundary,
and synchronous mode with DMA.
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