User`s guide

Chapter 1. Overview
EK–KZPBA–UG. B01 1–3
PCI Bus Interface
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Up to 132 MB/sec data transfer rate on the PCI bus
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PCI single and dual address cycles support
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PCI bus address and data parity generation
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PCI bus master for data transfer
SCSI-3 Implementation
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Concurrent support for asynchronous, Fast SCSI synchronous, and Ultra SCSI
synchronous devices
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Concurrent support for 8- and 16-bit SCSI devices
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Scatter/Gather
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Disconnect/Reconnect
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Fully multithreading/multitasking
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68-pin high density external connector
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One 68-pin high density and one 50-pin internal connectors
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Tagged Queuing
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Support of multiple LUNs
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SCSI termination power control
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Parity handling in Data, Message, Status, Selection/Reselection, and
Command phases
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Active negation
Maximum Off-loading of Host CPU Requirements
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Onboard RISC and SCSI executive processors automates SCSI processing
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Low SCSI processing overhead
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Bus Master DMA implementation
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Task scheduling and message-based communication