Specifications

3. Bus-indicates that a peripheral is controlling the bus. It is lit when
BBSY (Bus Busy) is asserted, unless the processor (which includes
the Console) is asserting BBSY.
4. Run-indicates that the processor is running. It monitors the cdntrol
flip-flop for the internal clock.
5. Source&ndicates that the central processor is. obtaining source
data except from an internal register.
6. Destination-indicates that the central processor is obtaining des
tination data (except from an internal register).
7. Address-identifies the source or destination address cycle of the
’ central processor, using two lights that are decoded zero, one, two,
or three. When references are made via the Unibus to the.addresses,
the lights tell the machine’s source or destination cycle. For an in-
ternal register reference, there is a “zeroth” addressing operation.
REGISTER DISPLAYS-The Operator’s Console has an l&bit Address Regis-
ter Display and a 16-bit Data Register Display. The Address Register Display
is tied directly to the output of an l&bit flip-flop register called the Bus
Address Register. This register displays the address of data examined or
deposited.
*The l&bit data register is divided on the face of the console by a line into
two 8-bit bytes. This register is tied to t,he output of the processor data paths
and will reflect the output of the processor adder.
SWITCH REGISTER-The PDP-ll/lO’and PDP-ll/PO can reference 216 bytes
addresses. However, the Unibus ,has expansion capability for 218 byte ad-
dresses. In order that the console can access the entire l&bit address
scheme, the switch register is 18 bits wide. These bits are assigned as 0
through 17. The highest two are used only as addresses. A switch in the
“up” position is considered to have a “1” value and in the “down” position
to .have a “0” value. The condition of the 18 switches can be loaded into the
bus address register or any memory location by using the appropriate control
switches which are described below.
.
CONTROL SWITCHES-The switches listed in item 5 of the “Console
Elements” have these specific control functions:,
1.
2.
3.
4.
5.
6.
7.
LOAD ADDR-transfers the contents of the l&bit switch register
into the bus address register.
EXAM-displays the contents of the location specified by the bus
address register.
DEP-deposits the contents of the low 16 bits of the switch register
into the address then displayed in the address register. (This switch
is actuated by raising it.)
ENABLE/HALT-allows or prevents running of programs. For a pro-
gram to run, theswitch must be in the ENABLE position (up). Placing
the switch in the HALT position (down) will halt the system.
START-starts executing a program when the ENABLE/HALT switch
is in the ENABLE position. When the START switch is depressed, it
asserts a system initialization signal; the system actually starts when
the switch is released. The processor will start executing at the
address which was last loaded by the LOAD ADDR key.
CONT-allows ‘the machine to continue without initialization from
whateyer state it was in when halted.
S/ INST-S/CYCLE-determines whether a single instruction or a
single bus cycle is performed when the CONT switch is depressed
while the machine is in the halt mode.
88
. .