Specifications

In addition to two Master Control circuits, a third logic network provides the
necessary signals and gating to perform the INTR bus operation. When either
of the START INTR signals is asserted, the INTR bus signal is asserted
along with a vector address qn D < 07:02 >. Bits 07:03 are determined by
jumpers on the card. A jumper “in” forces a 0 in that bit. Bit 2 is controlled
by Vector Bit 2. When the processor responds to the INTR signal by asserting
SSYN, the INTR DONE signal is asserted. This line is used to clear the
condition which asserted INTR START.
Figure 9.8 M782 Interrupt Control
Figure 9-9 shows a possible interconnection of the M782 to provide inde-
pendent interrupts for two possible conditions in a device: ERROR and DONE.
The ERROR and DONE signals shown in Figure 9-9 are signals from bits 15
and 7 in a device’s CSR. Likewise ERROR INT ENB and DONE INT ENB are
derived from the CSR. Both interrupts in this example are tied to the BR4
level: the corresponding grant line BG4 enters the ERROR Master Control and
is passed on to the DONE Master Control. Thus, ERROR ha% a slightly higher
priority interrupt level than DONE.
Both MASTER signals are tied to the INTR control. Thus, whenever either
ERROR or DONE gains bus control, an INTR operation is initiated. Note
that Vector Bit 2 is a 1 or 0 as a function of which master control
_ is interrupting. Also, INTR DONE is tied to MASTER CLEAR to clear the
master condition.