Specifications

EXT. CAP
I
-J f , 1 1 SELECT 2 H
EH
t
SELECT 4 H
SELECT 6 Ii
A62L
J
I
A61 L
AmL
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OUTHl6HH
GIL
OUT LW Ii
CaL a
IN tl
Figure 9.6 Ml05 Address Selector
M782 INTERRUPT CONTROL
4
The M782 Interrupt Control module contains the necessary logic circuits to
allow a peripheral device to gain bus control and perform a program inter-
rupt. The three circuits on this card are block diagrammed in Figure 9-8.
Note that only signals relevant to the user’s interface are shown; bus
signals SSYN, BBSY and SACK have been omitted for clarity.
The Master Control circuit is used to gain bus control. When INT and INT
ENB are asserted, a bus request is made on the request line to which BR
is jumpered. When the processor issues the corresponding grant and other
bus conditions are met, the MASTER signal is asserted, indicating that this
device now has bus control. Note that this circuit also can be used to gain
bus control on an NPR line for a device which requests the bus for direct
memory access.
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