Specifications

I
I
I
I
I
I
I
I
L-
M930
---
i WI--
-J
DRIVER
Rl , R2=190fi 5% 1/4W
R3. R4 = 390A 5% iI4W
Figure 9.2 Typical Unibus Line
Information is received from the bus using gates which have a high input
impedance and proper logic thresholds. High input levels must be greater
than 2.5 V with an input current less than 160 pa. Low level input must be
less than 1.4 V with an input current greater than 0 pa.
information transmitted on the bus must be driven with open collector drivers
capable of sinking 50 ma with a collector voltage of less than .8 V. Output
leakage current must be less than 25 ~a.
In PDP-11 systems, the bus signals are terminated at both ends by resistor
dividers provided on the M930 module. Physically, an M930 is located in
the processor; another is located at the last unit on the bus. A bus signal
sits at logical “0” (inactive, or negated state) at a voltage of 3.4 V. A bus
line is at logical “1” (active, or asserted) when it is pulled to ground.
Drivers and receivers meeting these specifications are available on the
M783, M784 and M785 modules as shown in Figures 9-3, 9-4 and 9-5.
70