Specifications

CHAPTER 9
Interfacing
A typical device bus interface as shown in Figure 9-l is composed of five
major components: 1). Registers; 2), Bus Drivers and Receivers; 3). Address
Selector; 4). interrupt Control; and 5), Device Control Logic.
REGISTERS
Each device is assigned bus addresses at which the program can inter-
rogate and/or load the device status, control, and data registers. The stan-
dardized mapping for these registers and the bit assignments of the corn- .
mandlstatus register (CSR) were given in Chapters 5 and 6.
As shown in Figure 9-1, all information flow between the device logic and ’
the Unibus is done through the registers. In general, registers are designed
to be both loadable and readable from the bus. This allows the program to
use such instructions as ADD RO, REG, or INC REG. However, registers can
be “one-sided,” either “read-only” or “write-only.” Examples of read-only
bits are the DONE and BUSY flags in the device’s CSR. These bits are de-
rived from the internal state of the device log& and are not under direct
program control. Write-only registers are used when it is unnecessary to
read back information. Attempting to read such a register would result in an .
all-zero transfer. The instructions effective with this type of register are then
limited to those which load the register such as MOV RO, REG, or CLR REG
(as opposed to ADD REG, RO, or INC REG).
Figure 9.1 Typical Peripheral Device Interface
BUS DRIVERS AND RECEIVERS
To maintain the transmission-line characteristics of the Unibus, special cir-
cuits are required to pass signals to and from the bus. The majority of bus
signals (all except the five grant lines) are received, driven and terminated
as shown in Figure 9-2.
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