Specifications

by negating BBSY. Bus control will then pass to either a device that was
selected in the meantime by another PTR sequence or back to the processor,
which will continue where it was interrupted. Active release of bus control
is realized through the INTR bussequence.
The INTR (interrupt) operation is used by the bus master to transfer to the
processor a memory address (called the interrupt vector). Two consecutive
words, the starting address of an interrupt service routine and a new status
word, are stored at the interrupt vector address. After the INTR sequence is
Complete, the Processor automatically becomes bus master and begins a trap
sequence in which it stores the current value of the PC and PS on the stack
and fetches a new PC and PS from the location pointed to by the interrupt
vector. Thus, the next instruction executed is the Start of, the interrupt
service routine.
It is illegal to issue an INTR command after gaining control of the bus by
requesting on an NPR line. NPR requests are granted during instruction
execution and external bus masters must restrict their bus use* to nonpro-
cessor activities.
Interrupt Servicing Sequence Example-The following is an example of the .*
INTR sequence.
, _
When a peripheral requires service and requests control of the bus with a
BR signal, the operations undertaken to “service” the device are as follows:
l Gain Control of the Bus-When the processor has no higher priority tasks
to complete, it relinquishes the bus to that device. Higher priority items are
(in order of priority):
1. Acknowledging an NPR request
2. Handling a processor error (illegal instructions, requirements for non-
existent memory, etc.)
3. Completing the current instruction
4. Acknowledging a trace trap
5. Continuing a higher priority process
6. Acknowledging a higher level BR signal
7. Acknowledging same level BR signals for devices closer to the processor
l Do INTR Sequence-when the device has cpntrol of the bus, it initiates
an INTR sequence, transferring to the processor the interrupt vector address
which specifies two words in memory containing the address and status of
the appropriate device service routine.
0 Push Old Interrupt Vector Onto Stack-The processor then “pushes”-
first, the current central processor status (PS) and then the current program
counter (PC) onto the processor stack.
l Fetch New Interrupt Vector-The new PC and PS (the “interrupt vector”)
are taken from the address specified by the device, and the device service
routine is begun. Note that those operations all occur automatically and that
no device polling is required to determine which service routine to execute.
Example of NPR Operation-Disk operation gives an example of a device
‘which uses the bus for direct memory access. Under program.control, the
processor would initialize registers in the disk control that specify word count
(WC, number of words in block of data to be transferred), memory address
(MA, the address at which the block of /data is found or is loaded), and Track
Address (TA, the point on the disk where the block of data starts). Also, the
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