Specifications
cessor status register. These three bits set a priority level that inhibits
granting of bus requests-on lower levels.
Second, bus requests from external devices can be
made on oni of five
request lines.
NPR has the
highest priority, and its request is honored by the
processor between bus cycles of an instruction execution. BR7 is the next
highest; BR4 is the lowest. These four lower level requests are honored by
the processor between instructions, except when the instruction currently
being executed causes an internal trap (either an error or trap instruction).
In this case, BR requests will not be honored until completion of the first
instruction after the trap sequence. Thus if two requests are made to the
processor for bus control, the higher of the two requests will be honored first.
Third, in response to a bus request, the processor may honor the request by
asserting a bus grant (BG) corresponding to the line on which the bus re-
quest was made. This signal is passed serially through each device in the
system. If a device had made a request, it would. block the grant signal
and prevent it from reaching the following devices. Thus, in this “pass-the-
pulse” chain, the device that is closest to the processor has the highest
~ priority on that request level.
This table lists device priorities:
Highest: Devices on NPR
Processor when priority = 111
Devices on BR7
Processor when priority = 110
Devices on BR6
Processor when priority =
101
Devices on BR5
Processor when priority =
100
Devices on BR4
Processor when priority =
011
Internal options
Processor when priority =
010
Internal options
I
Processor when priority =
001
Internal options
Lowest: Processor when priority = 000
When the processor’s priority is set at N, all requests for bus control at
level N and below are ignored.
SELECTION OF NEXT BUS MASTER-The signal sequence by which a device
becomes selected as next bus master is the PTR (Priority Transfer) bus ,
operation. Note that this operation does not actually transfer bus control:
it only selects a device as next bus master. It takes one additional condition
to complete the transfer: the current bus master must complete its bus
operations. The signal that indicates this is BBSY. Thus, when a device makes
an NP,R or BR request to the processor for bus control, it waits until it first
becomes selected as next bus master by the PTR operation and second, it
no longer senses BBSY, The negation of the BBSY signal indicates that
the current master has completed its bus operation. The selected device
now becomes bus master and asserts BBSY itself.
INTERRUPT SEQUENCE---Once the device has bus control and is asserting
BBSY itself, it‘is sole user of the bus until it releases its control. This release
of control can be made either actively or passively. Passive release is realized
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