Specifications

MASTER
\
SLAVE
OPERATION: DAl-0
A.C,D
MSYN ‘4
rg------ SSYN
A’C’D 3
I
SSYN
Figure 8-4(a)
The flow of signals for DATI is shown in Figure 8.4(b). (DATIP is similar
except that the internal operation of the slave device is modified.) The master
sets Control for DATI, sets Address for the slave to be se’lected, and asserts
MSYN. The selected slave responds by setting Data for the information re-
quested and asserts SSYN. The master sees SSYN, accepts the data, and
then negates Control, Address, and MSYN. The slave sees MSYN negated
and negates SSYN. The master continues when it sees SSYN negated.
A more detailed signal sequence for the DATI, DATIP, DATO, and DATOB bus
operations can be found in Appendix D.
MASTER
/
SLAVE
OPERATION: DATI
W
MSYN
i
, SSYNaD
v
$% _
ssVN6
i ’
Figure 8-4(b)
UNIBUS CONTROL OPERATIONS
The following section will deal with how a device becomes master of the bus
.and how control of the bus is transferred from one device to another. TWO
additional bus operations will be presented-the PTR (Priority Transfer) and
INTR (Interrupt).
In normal operation, the processor is bus master, fetching instructions and
operands from memory. Other devices on the bus have the capability of
becoming bus master, and use the bus for one of two purposes: l), to gain
direct memory access or 2). to interrupt program execution and force the
processor to branch to a specific address:
PRIORITY ARBITRATION-Transfer of bus control from one device to another
is determined by a priority scheme in which three factors must be considered.
First, the processor’s priority is determined by bits 7, 6, and 5 in the pro-
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