Specifications
I
instruction sequence will leave 10027 in location 500. In binary form, this
coding appears as:
1000: 105210
;INCB @RO
1002:
062710
;ADD (PC)+, @RO
1004: 000003
;3
. The following table lists the bus operations that result
of these two instructions:
Processor Cycle
Bus Operation
Bus Address
1. Fetch
DATI
(PC),=
001000
2. Destination
DATIP
(RO) = 000500
3.
Execute
DATOB
(RO) = 000500
4. Fetch DATI
(lqz) = 001002
5.
Source DATI (PC)=
001004
6. Destination
DATIP (RO) = 000500
7. Execute DATO
(RO) = 000500
as a consequence
Dais Transferred _
105210
010923
000024
062710
000003
010024
010027
Note that instep 3, it is inconsequential what data appears on D < 15:OB >;
the slave accepts only the modified low byte.
A second example of bus ‘operation compares the contents of the Teletype
keyboard data buffer whose address is 177560 with the ASCII value for the
letter “A.”
200:
CMPB @#177560, #301
This instruction is assembled in three words as follows:
200: 123727
;CMPB @@7)+, WV+
202: 177560
;Address of data buffer
204: 000301 ;301
The processor will execute this instruction with these cycles:
Processor Cycle Bus Operation
Bus Address Data Transferred
1.
Fetch DATI
(PC) = 200 123727 ’
2.
Source DATI
(PC)=202 177560
3.
Source DATI
777560
ASCII
4. Destination DATI
(PC) = 204 000301
5. Execute none -
condition codes set internally.
Note that in step 3, the soware specified address 177560 was converted to
the
bus
address 777560.
SIGNAL DESCRIPTION OF DATA TRANSFERS-Figure 8.4(a) shows the sig
nal flow between master and slave during a DATO operation. (The sequence
is similar for DATOB except that only a byte of information is transferred.)
The master sets Control for DATO, sets Address for the unique slave address,
and sets Data for the information to be transferred. The master then asserts
MSYN. This signal is received by the slave that recognizes its address: it
responds by accepting the data
arid
asserting SSYN. SSYN is received by the
master which then negates Control, Address, Data, and MSYN. The slave
sees MSYN negated and negates SSYN. The master device continues its
operation when it sees SSYN negated.
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