Specifications

.
scFrwAF& AOORESS HAROWARE ADDRESS
oooo#O-017777
trt 4K
MEMORY BANK
02CWO-037777
El
oooooo-own7
02ooOO-037777
2nd 4K
MEMORY 0Aw
I
I
I I
t40000-t57777 t40000-157777
7th 4K
MEMORY BANK _
t6oooo-t77777
El
760000-777777
PERIPHERAL
BANK
Figure 8-2 Address Map
.
The peripheral bank is composed of the processor’s fast memory, status
register, console switch register, and all device registers.
Control Lines (C < 1:0 > )-These two bus signals are coded by the master
device to indicate to the slave one of four possible data transfer operations.
Master Synchronization and Slave Synchronization (MSYN, SSYN)-MYSN
is a control signal used by the master to indicate to the slave that address
and control information is present. SSYN is the slave’s response- to MSYN
lnititiliiation (INIT)-This signal is a power clear signal asserted by the con-
sole and the processor which is used to reset peripheral devices.
PA, PB. SPl. SP2-These lines are not implemented on the PDP-ll/lO or
PDP-ll/PO.
INTERRUPT SIGNALS
Bus Request Lines (BR i: 7:4 > )-These four bus signals are used by
peripheral devices to request control of the bus.
Bus Grant Lines (BG < 7:4 >-)-These signals are the processor’s response
to a BR. They will be asserted only at the end of instruction execution.
Non-Processor Request (NPR)-This is a bus request from -a peripheral
device to the processor.
Non-Processor Grant (NPG)-This isthe processor’s response to an NPR. It
occurs at the end of bus cycles within the instruction execution.
Selection Acknowledge (SACK)-SACK is asserted by a bus-requesting device
that has received a bus grant. Bus control will pass to this device when the
current master of the bus completes its operations.
INTERRUPT (INTR)-This signal is asserted by the master to start program
interruption in the processor.
Bus Busy (BBSY)-This signal denotes bus in use by a master device.
UNIBUS DATA TRANSFER OPERATIONS
Direction of data transfers on the Unibus is defined in relation to the master
61