Specifications

the bus to communicate with other devices, call,ed slaves, on the bus. An
example of this relationship is the processor (master) fetching an instruction
from memory (which is always a slave).
INTERLOCKED COMMUNICATION-For erich control signal issued by the
master device, there is a response from the slave; thus bus communication
is independent of the physical bus length and the response time of the mas-
ter and slave devices. Also, master-slave relationships can exist in nearly
any combination between fast-responding and slow-responding devices.
*
DYNAMIC MASTER-SLAVE RELATION-Master-slave relationships are dy-
namic. The processor, for example, can pa&s bus control to a disk. The disk,
as master, could then communicate with a slave memory bank.
UNIBUS SIGNALS
The 56 Unibus signals can be divided into two major groups-the interrupt
group and the non-interrupt group. The interrupt group can then be sub-
divided into two classes-the request and control class and the grant class.
All bus signals except the grant class are bidirectional in nature and are
% connected to every device (though they may not be used by every device).
The grant signals, because of their special nature in priority bus control
(to be explained later), are bussed through each device and are unidiiectional
in nature.
NON-INTERRUPT SIGNALS
Data Lines (0 < 15:OO >)-(Note that the notation A <a:b> specifies
b - a + 1 signal lines which are named Aa through Ab.) The 16 data lines
are used to transfer information between master and slave. This is the bit
format:
I HIGH BYTE I LOW BYTE 1
(5
8 7 0
Address Lines (A < 17:00 >)-The 18 address lines are used by the master
device’to select the slave (a unique core memory or device register address)
with which it will be communicating. This is the bit format of the 18 signals:
A < 15:Ol > are used to specify a unique 16-bit word group. In byte opera-
tions, A00 is used to specify the byte being referenced. If a word is refer-
enced at X (X must be even, since words can be addressed on even bound-
aries only), the low byte can be referenced at X and the high byte at X + 1.
A < 15:00 > are supplied by the software as memory reference addresses.
Al7 and Al6 are used as extended memory bits for relocation and as pro-
tection schemes in future systems. In the PDP-11/20 and the PDP-ll/lO,
Al7 and Al6 are asserted or forced to 1 whenever an attempt is made to
reference a memory location where A15’= Al4 = Al3 = 1. Thus the hard-
ware converts the 18bit software address to a full Is-bit-bus address.
An address map is shown in Figure 8-2.
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