Specifications

A tvoical set might be:
_.
1. Control-and status register
2. Memory address register
3. Word count register
4. Device address register
Loading the device address register would in general initiate the transfer,
which then proceeds without processor intervention. The device issues non-
processor requests for the Unibus that, when granted, allow direct data
transfer between the device and memory. These requests are interleaved
with processor. requests for the bus. If very fast transfer is required, the
processor may execute a WAIT instruction after starting the block transfer.
The DONE or appropriate -error bits are set in the CSR with Completion of
the transfer or when an error occurs. These may be enabled to cause an
interrupt or may be tested to determine when the device needs assistance.
A block transfer could be executed as follows:
’ MOV #401, DKS, ; read block of data (function 1)
; from unit 1
MOV #BUFADR, DKMA
; buffer address to memory ad-
; dress register
MOV #BUFCNT, DKWC ; word count to word count register
MOV #BLKNO, DKDA ; block number to device address
; register, which starts the trans-
; fer
.
: when data is needed.
LOOP: BIT #DKMSK, DKS
; test done bit and error bits
BEQ LOOP ; branch back if none on \
BIT #DKEMSK, DKS
; test for any error bits
BNE ERROR
; branch if any on
; data is now in buffer at BUFADR
INTERRUPT STRUCTURE
If the appropriate interrupt enable bit is on, in,the control and status register
of a device, transition from 0 to 1 of the DONE or READY bit causes an
interrupt request to be issued to the processor. Also if DONE or READY’ is a
_
1 when the interrupt enable is turned on, an interrupt request is made. If
the device makes the request at a priority greater than that at which the
processor is running and no other conflicts exist, the request is granted and
the interrupt sequence takes place:
a. the current program counter and processor status are pushed onto
the processor stack;
.b. the new PC and PS are loaded from a pair of locations (the interrupt
vector) in low core unique to the interrupting device.
Since each device has a unique interrupt vector which dispatches control to
the appropriate interrupt handling routine immediately, no device polling is
required.. Furthermore, since the PS contains the processor priority, the
priority at which an interrupt request is serviced can be set under program
control and is independent of the priority of the interrupt request. The
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