Specifications

acter. Incrementing the PRS will set bit 0 and cause one character to be
read. The instruction
INC
PRS
performs that function. MOV #l, PRS does the same thing but takes one
more word.
DATA BUFFER REGISTERS-Each device has at least one buffer register
for temporarily storing data to be transfer into or out of the computer. The
number and type of data registers is a function of the device. The paper
tape reader and punch use single 8-bit data buffer registers. A disk would
use I&bit data registers and some devices may use two ldbit registers for
data buffers.
PROGRAMMING EtiMPLES
PROGRAM CONTROLLED DATA TRANSFER WITH THE INTERRUPT DISABLED
-Single character I/O devices (teletype, paper tape reader/punch) have an
addressable register buffer through which data is transferred. For input, the
data buffer register is the source operand of the instruction used to get the
.
data; for output, it% the destination operand. For example assuming the
paper tape reader interrupt is not enabled, character input could proceed
as follows:
MOV R, -(SP)
; save R on the stack
MOV #8UFFER, R
; pointer to input buffer into register R
START: INC PRS
; start up reader
LOOP: BIT PRS, # 100200 ; test DONE and ERROR bits
BEQ LOOP
; branch back if none on yet
BMI ERROR ; branch to error routine if minus
MOVB PRB, (R)+ ; move byte from device buffer reg-
;
ister to user’s buffer and increment
; pointer
CMP #LIMIT R, ; check for end of buffer
BGE START ; get next character.
MOV (SP)+, R
;
restore R
-
Character output to the paper tape punch might be executed as follows:
LOOP:
MOV RO, L(SP)
MOV Rl, -(SP)
MOV NCHAR, RO
MOV BUFFER, Rl
BIT PPS, #100200
BEQ LOOP
BMI ERROR
MOVB (Rl)+, PPB
DEC RO
BGT LOOP
MOV (SP)+, RO
MOV (SP)+, Rl
;
save RO
;
save Rl
; *number of characters into RO
; user buffer address into Rl
; test device ready and error bits
; fall through if on
; branch on error
; output character, increment pointer
; decrement character counter (and
; set condition codes)
; repeat if greater than zero
; restore RO
; restore Rl
BLOCK
TRANSFER WITH THE INTERRUPT DISABLED-High-speed block
transfer devices use the Unibus to make data transfers between the device
and core memory. These devices are provided with addressible registers
that control the flow of data.
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