Specifications

in Figure 5-1. Three areas of addresses of particular interest to the Pro-
grammers are: 1) Interrupt and Trap VeMors; 2) Processor Stack and General
Storage; and 3) Peripheral Device Registers.
INTERRUPT AND TRAP VECTORS-Addresses between lOCatiOn zero and
location 4001 are generally reserved for interrupt and trap vectors.
PROCESSOR STACK AND GENERAL STORAGE-Addresses between 4001
and the limit of implemented core are available for the processor stack or
other programs and data. The highest address in ttiis region is 157777*.
PERIPHERAL DEVICE REGISTERS-Addresses above 160000, generally are
reserved for peripheral device status, control, and data registers. The general
registers and the processor status can be addressed from the program
console using addresses in this area.
A more detailed address allocation map can be found in Appendix D.
CORE MEMORY
The three types of core memory that can be used in a PDP-11 system are:
1) Read-Write Core Memory: 2) Read-Only Core Memory; and 3) Wordlet
Memory. These memories can be located anywhere in address space provided
they do not overlap. They do not have to be in continuous address locations.’
MMll-E READ WRITE CORE MEMORY-The MMll-E has the following
specifications:
,
Capacity: 4,096 l&bit words or 8,192 8-bit bytes -
Cycle Time: 1.2 microseconds
Access Time: 500 nanoseconds
Configuration: Planer 3-wire, 3-D using 22 mil cores
Packaging: One standard PDP-11 System Unit
interface: Designed to work with PDP-11 bus, l-FL-compatible
MRll-A READ-ONLY CORE MEMORY (ROM)-The ROM has the following
specifications:
Capacity: 1,024 l&bit words or 2,048 8-bit bytes
Access Time: 500 nanoseconds
Configuration: P-piece core with wire braid, 256 wires, 64 cores
Packaging: 3/4 of one standard PDP-11 System Unit
Interface: Designed to work with PDP-11 bus, TTL-compatible
MWllA WORDLET MEMORY-The wordlet memory is used with ROM sys-
tems and provides read-write memory capacity for temporary data and in- ’
struction storage.
Capacity: 128 16.bit words or 256 8-bit bytes
Cycle Time: 2.0 microseconds
Access Time: 1.0 miorosecond
Configuration: 5-Wire, 3D
Packaging: l/4 standard PDP-11 single System Unit-
Interface: The wordlet memory will work with the ROM and interfaces
through the ROM System Unit to the PDP-11 bus.
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