Specifications

An instruction that set the T-bit-Since the T-bit was already set, Settiflg it
again has no effect.
An instruction that caused an Instruction Trap--The instruction trap is
sprung and the entire routine for the service trap is executed. If the service
routine exists with an RTI or in any other way restores the stacked status
word, the T-bit is set again, the instruction following the traced instruction
is executed and, unless it ,is one of the special cases noted above, a trace
trap occurs.
An instruction that caused a Bus Error-This is treated as in an Instruction
Trap. The only difference is that the error service is not as likely to exit
with an RTI, so that the trace trap may not occur.
An instruction that caused a stack overflow-The instruction COmpleteS
execution as usual-the Stack Overflow does not cause a trap. The Trace
Trap Vector is loaded into the PC and PS, and the old PC and, PS are pushed
onto the stack. Stack Overflow occurs again, and this time the trap is made.,
An interrupt between setting of the T-bit and fetch of the traced instruction
The entire interrupt service routine is executed and then the T-bit is set again
by the exiting RTI. The traced instruction is executed (if there have been no
other interrupts) and, unless it is a special case noted above, causes a trace
trap.
Note’that no interrupts are acknowledged between the time of fetching any
trapped instruction (including one that is trapped by reason of the T-bit being
set) and completing execution of the first instruction of the trap service.
A WAIT-The trap occurred immediately. The address of the next instruction
is saved on the stack.
.
A HALT-The processor halts. When the continue. key on the console is
pressed, the instruction following,the HALT is fetched and executed. Unless
it is one of the exceptions noted above, the trap occurs immediately follow-
ing execution.
Trap priorities-In case multiple processor trap conditions occur simultane-
ously the following order of priorities is observed (from high to low):
1. Bus Errors
2. instruction Traps
3. Trace Trap
4. Stack Overflow Trap
The details on the trace trap process have been described in the trace trap
operational description which includes cases in which an instruction being
traced causes a bus error, instruction trap, or a stack overflow trap,
If a bus error is caused by the.trap process handling instruction traps, trace
traps, stack overflow traps, or a previous bus error, the processor is halted.
If a stack overflow is caused by the trap process in handling bus errors, in-
struction traps, or trace traps, the process is completed and then the stack
overflow trap is sprung.
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