Specifications
R.Turn from Interrupt RTI
4.Bus
/
01 ,o, I IO, I 101 I 101 I a21
IS
0
Operation: SP T (PC), SP t (PS).
Condition Codes: loaded from processor stack.
Description: Used to exit from an interrupt or TRAP service routine. The PC
and PS are restored (popped) from the processor stack.
Instruction traps are also caused
by
attempts to execute instruction codes
reserved for future processor expansion (reserved instructions) ‘Or instruc-
tions with illegal addressing modes (illegal instructions). Order codes not
corresponding to any of the instructions described above are considered to
be reserved instructions. Illegal instructions are JMP and JSR with register
mode destinations. Reserved and illegal instruction traps occur as described
under EMT, but trap through vectors at addresses
10
and 04 respectively.
Stack Overflow Trap-Stack.Overflow Trap is a processor trap through the
vector at address 4. It is caused by referencing addresses below 400, through
,
the processor
stack
pointer R6 (SP) in autodecrement or autodecrement de-
ferred addressing. The instruction causing the overflow is completed before
the trap is made.
Bus Error Traps-Bus Error Traps are:
1.
Boundary Errors-attempts to reference word operands at odd ad-
dresses.
2. Time-Out Errors-attempts to reference
addresses on
the bus that
made no response within 10 ps. In general, these are caused by at-
tempts to reference nonexistent memory, and attempts to referf?nce
nonexistent peripheral devices.
Bus error traps cause processor traps through the trap vector address 4.
Trace Trap-Trace Trap enables
bit
4 of the PS word and causes processor -
traps at the
end
of instruction executions. The instruction that is executed
after the instruction that set the T-bit will proceed to completion and then
cause a processor trap through the trap vector at address 14.
The following are special
cases and
are detailed in subsequent paragraphs.
1.
The traced instruction cleared the T-bit.
2. The traced instruction set the T-bit.
3. The traced instruction caused an instruction trap.
4. The traced instruction caused a bus error trap.
5. The traced instruction caused a stack overflow trap.
6. The process was interrupted between the time the T-bit was set and
the fetching of the instruction that was to be traced.
7. The traced instruction was a WAIT.
8. The traced instruction was a HALT.
I
An instruction that cleared the T-bit-Upon fetching the traced instruction
an internal flag, the trace flag, was set. The trap will still occur at the end
of execution of this instruction. The stacked status word, however, will have
a clear T-bit.
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