Specifications

Combinations of the above set or clear operations may be ORed together to
form new instruction mnemonics. For example: CLCV = CLC ! CLV. The new
instruction clears C and V bits. (‘I!”
signifies “inclusive or” in PAL-11.)
MISCELLANEOUS CONTROL iNSTRUCTIONS
RESet ExTernol bus
RESET
20 ms
01
IO,
I 101 I 101 I lOI I I 5 ,
15
0
Condition Codes: not affected
Description: Sends an INIT pulse along the Unibus by the processor. AlI
devices on the bus are reset to their state at power-up.
\
WAit for IntempT
WAIT 1.8 IL*
15
Condition Codes: not affected
0
Description: Provides a way for the processor to relinquish use of the bus
while it waits for an external interrupt. Having been given a WAIT command,
the processor will not compete for bus use by fetching instructions or
operands from memory. This permits higher transfer rates between a device
and memory, since no processor-induced latencies will be encountered by
bus requests from the device. In WAIT, as in all instructions, the PC points
to the next instruction following the WAIT operation.
Thus when an interrupt causes the PC and PS to be pushed onto the proces-
sor stack, the address of the next instruction following the WAIT is saved.
The exit from the interrupt routine (i.e. execution of an RTI instruction) will
cause resumption of the interrupted process at the instruction following the
WAIT.
HALT
HALT
l.SlLS
01 101 I IO, I ,Ol I 101 I 101
45 0
Condition Codes: not affected
Description: Causes the processor operation to cease. The console is given
control of the bus. The console data lights display the contents of RO; the
console address lights display the address of the halt instruction. Transfers
on the Unibus are terminated immediately. The PC points to the next in-
struction to be executed. Pressing the continue key on the console causes
processor operation to resume. No INIT signal is given.
Processor Traps -Processor Traps are internally generated interrupts.
Error conditions, completion of an instrustion in trace mode (i.e. T-bit of
status word set), and certain instructions cause traps. As in interrupts, the
current PC and PS are saved on the processor stack and a new PC and PS
are loaded from the appropriate trap (interrupt) vector. See Appendix C for
a summary of Trap Vector Addresses.
,Trapf Instructions-Trap Instructions provide for calls to emulators, i/O
monitors, debugging packages, and user-defined interpreters.
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