Specifications
Double precision norma’lization proceeds similarly: ,
DNORM:
ASL A0
; double precision left shift
ROL Al
BEQ
DZERO ; high order result O?. if
so, check.10~
BVC DNORM ; if the sign did not change, continue
ROR Al ; restore the sign
BR \ DNDONE ; normalization complete
DZERO:
TST A0 ; low order zero, too?
BNE DN0RM
; if not, continue normalization
ROR Al ; restore the sign; 000000 or 100000
ASR Al
; and replicate it; 000000 or 140000
DNDONE: :. .
The following example illustrates the use of shifts and rotates in a 16-bit un-
signed integer multiply subroutine. Access of operands through address
parameters following the subroutine is also shown. The multiplication takes
115170 &s in in-line code. The entire subroutine as shown below takes
approximately 200 ps and requires 16 words. The calling sequence is JSR
R5, MULT.
I
. WORD MCAND ; address of multiplicand
,
. WORD MPLIER ; address of multiplier
. WORD PROD ;.address of product
MULT: CLR RO
MOV @ (R5) +, Rl ; get multiplier into Rl
MOV @ (R5) +, R2
; get multiplicahd into R2
MOV #-169 R3 ; set counter
M LOOP: ASL RO ; double prec shift
ROL Rl
BCC NOADD
ADD R2, RO
ADC Rl
NOADD: INC R3
BNE MLOOP
MOV (R5) +, R2
MOV RO, (R2) +
MOV Rl, (R2)
RTS R5
; shift and add multiply
; most significant bit governs add
; if set add in multiplicand
; keep 32-bit product
; done?
; if not continue
; get address to store prod.
; put low-order away, move to high
; put high-order away
; return to calling program
Bni OPERATIONS--The PDP-11 processor includes a full complement of
instructions that manipulate byte operands. Addressing is byte-oriented so
that instructions for byte manipulation are straightforward. In addition, byte
instructions with autoincrement or autodecrement direct addressing cause
the specified register to be stepped by one to point to the next byte of data.
Byte operations in register mode access the low-order byte of the specified
register. These provisions enable the PDP-11 to perform as either a word or
byte processor.
Timing of byte instructions is the same as for word instructions except that
an additional 0.6 ps is required for access of bytes at odd addresses.
Double Operand Byte Instructions-
Move !sytr
MOVB WC, dst 2.3~
WC
dst
1 , t
I I I I I I I’, I I I I I
. 15
t2 11 6 5 0
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